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/Zephyr-latest/samples/shields/x_nucleo_53l0a1/src/
Ddisplay_7seg.h25 #define CHAR_0 (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
26 #define CHAR_1 (BIT(5) | BIT(6))
27 #define CHAR_2 (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(5))
28 #define CHAR_3 (BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
29 #define CHAR_4 (BIT(1) | BIT(2) | BIT(5) | BIT(6))
30 #define CHAR_5 (BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(6))
31 #define CHAR_6 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(6))
32 #define CHAR_7 (BIT(3) | BIT(5) | BIT(6))
33 #define CHAR_8 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
34 #define CHAR_9 (BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
[all …]
/Zephyr-latest/tests/kernel/common/src/
Dbitfield.c14 #define BIT_INDEX(bit) ((3 - ((bit >> 3) & 0x3)) + 4*(bit >> 5)) argument
16 #define BIT_INDEX(bit) (bit >> 3) argument
18 #define BIT_VAL(bit) (1 << (bit & 0x7)) argument
41 unsigned int bit; in ZTEST()
46 for (bit = 0U; bit < 32; ++bit) { in ZTEST()
47 sys_set_bit((mem_addr_t)&b1, bit); in ZTEST()
49 zassert_equal(b1, (1 << bit), in ZTEST()
50 "sys_set_bit failed on bit %d\n", bit); in ZTEST()
52 zassert_true(sys_test_bit((mem_addr_t)&b1, bit), in ZTEST()
53 "sys_test_bit did not detect bit %d\n", bit); in ZTEST()
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/Zephyr-latest/drivers/sensor/st/lsm9ds0_mfd/
Dlsm9ds0_mfd.h22 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMOR BIT(7)
24 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMOR BIT(6)
26 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMOR BIT(5)
28 #define LSM9DS0_MFD_MASK_STATUS_REG_M_XMOR BIT(4)
30 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMDA BIT(3)
32 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMDA BIT(2)
34 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMDA BIT(1)
36 #define LSM9DS0_MFD_MASK_STATUS_REG_M_XMDA BIT(0)
50 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_XMIEN BIT(7)
52 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_YMIEN BIT(6)
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/Zephyr-latest/drivers/sensor/st/lsm9ds0_gyro/
Dlsm9ds0_gyro.h23 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_DR (BIT(7) | BIT(6))
25 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_BW (BIT(5) | BIT(4))
27 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_PD BIT(3)
29 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_ZEN BIT(2)
31 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_XEN BIT(1)
33 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_YEN BIT(0)
37 #define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPM (BIT(5) | BIT(4))
39 #define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPCF (BIT(3) | BIT(2) | BIT(1) | \
40 BIT(0))
43 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I1_INT1 BIT(7)
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/Zephyr-latest/drivers/sensor/st/lsm6dsl/
Dlsm6dsl.h29 #define LSM6DSL_MASK_FUNC_CFG_EN BIT(7)
31 #define LSM6DSL_MASK_FUNC_CFG_EN_B BIT(5)
35 #define LSM6DSL_MASK_SENSOR_SYNC_TIME_FRAME_TPH (BIT(3) | BIT(2) | \
36 BIT(1) | BIT(0))
40 #define LSM6DSL_MASK_SENSOR_SYNC_RES_RATIO (BIT(1) | BIT(0))
44 #define LSM6DSL_MASK_FIFO_CTRL1_FTH (BIT(7) | BIT(6) | \
45 BIT(5) | BIT(4) | \
46 BIT(3) | BIT(2) | \
47 BIT(1) | BIT(0))
51 #define LSM6DSL_MASK_FIFO_CTRL2_TIMER_PEDO_FIFO_EN BIT(7)
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/Zephyr-latest/drivers/audio/
Dtas6422dac.h18 #define MODE_CTRL_RESET BIT(7)
19 #define MODE_CTRL_RESET_MASK BIT(7)
20 #define MODE_CTRL_PBTL_CH12 BIT(4)
21 #define MODE_CTRL_PBTL_CH12_MASK BIT(4)
22 #define MODE_CTRL_CH1_LO_MODE BIT(3)
23 #define MODE_CTRL_CH1_LO_MODE_MASK BIT(3)
24 #define MODE_CTRL_CH2_LO_MODE BIT(2)
25 #define MODE_CTRL_CH2_LO_MODE_MASK BIT(2)
29 #define MISC_CTRL_1_HPF_BYPASS BIT(7)
30 #define MISC_CTRL_1_HPF_BYPASS_MASK BIT(7)
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/Zephyr-latest/drivers/sensor/apds9960/
Dapds9960.h14 #define APDS9960_ENABLE_GEN BIT(6)
15 #define APDS9960_ENABLE_PIEN BIT(5)
16 #define APDS9960_ENABLE_AIEN BIT(4)
17 #define APDS9960_ENABLE_WEN BIT(3)
18 #define APDS9960_ENABLE_PEN BIT(2)
19 #define APDS9960_ENABLE_AEN BIT(1)
20 #define APDS9960_ENABLE_PON BIT(0)
32 #define APDS9960_PERS_PPERS (BIT(4) | BIT(5) | BIT(6) | BIT(7))
33 #define APDS9960_APERS_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
36 #define APDS9960_CONFIG1_WLONG BIT(1)
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/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_ecia.h25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
27 BIT(26))
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
31 BIT(21) | BIT(23))
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
58 * BLOCK_ACTIVE registers: GIRQ8 is bit[8], ..., GIRQ26 is bit[26].
60 * Each GIRQ is composed of 5 32-bit registers.
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Dmec172x_i2c_smb.h36 * Size 8-bit
40 #define MCHP_I2C_SMB_CTRL_ACK BIT(0)
41 #define MCHP_I2C_SMB_CTRL_STO BIT(1)
42 #define MCHP_I2C_SMB_CTRL_STA BIT(2)
43 #define MCHP_I2C_SMB_CTRL_ENI BIT(3)
45 #define MCHP_I2C_SMB_CTRL_ESO BIT(6)
46 #define MCHP_I2C_SMB_CTRL_PIN BIT(7)
49 #define MCHP_I2C_SMB_STS_NBB BIT(0)
50 #define MCHP_I2C_SMB_STS_LAB BIT(1)
51 #define MCHP_I2C_SMB_STS_AAS BIT(2)
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/Zephyr-latest/drivers/ethernet/
Deth_dwmac_priv.h97 #define MAC_CONF_ARPEN BIT(31)
99 #define MAC_CONF_IPC BIT(27)
101 #define MAC_CONF_GPSLCE BIT(23)
102 #define MAC_CONF_S2KP BIT(22)
103 #define MAC_CONF_CST BIT(21)
104 #define MAC_CONF_ACS BIT(20)
105 #define MAC_CONF_WD BIT(19)
106 #define MAC_CONF_BE BIT(18)
107 #define MAC_CONF_JD BIT(17)
108 #define MAC_CONF_JE BIT(16)
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/Zephyr-latest/drivers/sensor/st/lps25hb/
Dlps25hb.h26 #define LPS25HB_MASK_RES_CONF_AVGT (BIT(3) | BIT(2))
28 #define LPS25HB_MASK_RES_CONF_AVGP (BIT(1) | BIT(0))
32 #define LPS25HB_MASK_CTRL_REG1_PD BIT(7)
34 #define LPS25HB_MASK_CTRL_REG1_ODR (BIT(6) | BIT(5) | BIT(4))
36 #define LPS25HB_MASK_CTRL_REG1_DIFF_EN BIT(3)
38 #define LPS25HB_MASK_CTRL_REG1_BDU BIT(2)
40 #define LPS25HB_MASK_CTRL_REG1_RESET_AZ BIT(1)
42 #define LPS25HB_MASK_CTRL_REG1_SIM BIT(0)
46 #define LPS25HB_MASK_CTRL_REG2_BOOT BIT(7)
48 #define LPS25HB_MASK_CTRL_REG2_FIFO_EN BIT(6)
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/Zephyr-latest/soc/neorv32/
Dsoc.h21 #define NEORV32_SYSINFO_CPU_ZICSR BIT(0)
22 #define NEORV32_SYSINFO_CPU_ZIFENCEI BIT(1)
23 #define NEORV32_SYSINFO_CPU_ZMMUL BIT(2)
24 #define NEORV32_SYSINFO_CPU_ZBB BIT(3)
25 #define NEORV32_SYSINFO_CPU_ZFINX BIT(5)
26 #define NEORV32_SYSINFO_CPU_ZXSCNT BIT(6)
27 #define NEORV32_SYSINFO_CPU_ZXNOCNT BIT(7)
28 #define NEORV32_SYSINFO_CPU_PMP BIT(8)
29 #define NEORV32_SYSINFO_CPU_HPM BIT(9)
30 #define NEORV32_SYSINFO_CPU_DEBUGMODE BIT(10)
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/Zephyr-latest/drivers/sensor/st/lsm6ds0/
Dlsm6ds0.h19 #define LSM6DS0_MASK_ACT_THS_SLEEP_ON_INACT_EN BIT(7)
21 #define LSM6DS0_MASK_ACT_THS_ACT_THS (BIT(6) | BIT(5) | BIT(4) | \
22 BIT(3) | BIT(2) | BIT(1) | \
23 BIT(0))
29 #define LSM6DS0_MASK_INT_GEN_CFG_XL_AOI_XL BIT(7)
31 #define LSM6DSO_MASK_INT_GEN_CFG_XL_6D BIT(6)
33 #define LSM6DS0_MASK_INT_GEN_CFG_XL_ZHIE_XL BIT(5)
35 #define LSM6DS0_MASK_INT_GEN_CFG_XL_ZLIE_XL BIT(4)
37 #define LSM6DS0_MASK_INT_GEN_CFG_XL_YHIE_XL BIT(3)
39 #define LSM6DS0_MASK_INT_GEN_CFG_XL_YLIE_XL BIT(2)
[all …]
/Zephyr-latest/drivers/sensor/st/lps22hb/
Dlps22hb.h22 #define LPS22HB_MASK_INTERRUPT_CFG_AUTORIFP BIT(7)
24 #define LPS22HB_MASK_INTERRUPT_CFG_RESET_ARP BIT(6)
26 #define LPS22HB_MASK_INTERRUPT_CFG_AUTOZERO BIT(5)
28 #define LPS22HB_MASK_INTERRUPT_CFG_RESET_AZ BIT(4)
30 #define LPS22HB_MASK_INTERRUPT_CFG_DIFF_EN BIT(3)
32 #define LPS22HB_MASK_INTERRUPT_CFG_LIR BIT(2)
34 #define LPS22HB_MASK_INTERRUPT_CFG_PL_E BIT(1)
36 #define LPS22HB_MASK_INTERRUPT_CFG_PH_E BIT(0)
43 #define LPS22HB_MASK_CTRL_REG1_ODR (BIT(6) | BIT(5) | BIT(4))
45 #define LPS22HB_MASK_CTRL_REG1_EN_LPFP BIT(3)
[all …]
/Zephyr-latest/include/zephyr/arch/arm64/
Dcpu.h13 #define DAIFSET_FIQ_BIT BIT(0)
14 #define DAIFSET_IRQ_BIT BIT(1)
15 #define DAIFSET_ABT_BIT BIT(2)
16 #define DAIFSET_DBG_BIT BIT(3)
18 #define DAIFCLR_FIQ_BIT BIT(0)
19 #define DAIFCLR_IRQ_BIT BIT(1)
20 #define DAIFCLR_ABT_BIT BIT(2)
21 #define DAIFCLR_DBG_BIT BIT(3)
23 #define DAIF_FIQ_BIT BIT(6)
24 #define DAIF_IRQ_BIT BIT(7)
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/Zephyr-latest/include/zephyr/math/
Dilog2.h25 * This calculates the floor of log2 (integer log2) for 32-bit
42 (((n) & BIT(31)) == BIT(31)) ? 31 : \
43 (((n) & BIT(30)) == BIT(30)) ? 30 : \
44 (((n) & BIT(29)) == BIT(29)) ? 29 : \
45 (((n) & BIT(28)) == BIT(28)) ? 28 : \
46 (((n) & BIT(27)) == BIT(27)) ? 27 : \
47 (((n) & BIT(26)) == BIT(26)) ? 26 : \
48 (((n) & BIT(25)) == BIT(25)) ? 25 : \
49 (((n) & BIT(24)) == BIT(24)) ? 24 : \
50 (((n) & BIT(23)) == BIT(23)) ? 23 : \
[all …]
/Zephyr-latest/drivers/ieee802154/
Dieee802154_mcr20a_regs.h11 * which are used in the macros for the bit field manipulation.
47 #define MCR20A_REG_READ (BIT(7))
48 #define MCR20A_BUF_READ (BIT(7) | BIT(6))
49 #define MCR20A_BUF_BYTE_READ (BIT(7) | BIT(6) | BIT(5))
51 #define MCR20A_BUF_WRITE (BIT(6))
52 #define MCR20A_BUF_BYTE_WRITE (BIT(6) | BIT(5))
119 #define MCR20A_IRQSTS1_RX_FRM_PEND BIT(7)
120 #define MCR20A_IRQSTS1_PLL_UNLOCK_IRQ BIT(6)
121 #define MCR20A_IRQSTS1_FILTERFAIL_IRQ BIT(5)
122 #define MCR20A_IRQSTS1_RXWTRMRKIRQ BIT(4)
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/Zephyr-latest/drivers/can/
Dcan_mcp251xfd.h89 #define MCP251XFD_REG_CON_ABAT BIT(27)
100 #define MCP251XFD_REG_CON_TXQEN BIT(20)
101 #define MCP251XFD_REG_CON_STEF BIT(19)
102 #define MCP251XFD_REG_CON_SERR2LOM BIT(18)
103 #define MCP251XFD_REG_CON_ESIGM BIT(17)
104 #define MCP251XFD_REG_CON_RTXAT BIT(16)
105 #define MCP251XFD_REG_CON_BRSDIS BIT(12)
106 #define MCP251XFD_REG_CON_BUSY BIT(11)
112 #define MCP251XFD_REG_CON_WAKFIL BIT(8)
113 #define MCP251XFD_REG_CON_PXEDIS BIT(6)
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/Zephyr-latest/drivers/gpio/
Dgpio_ite_it8xxx2.c35 /* gpio port data register (bit mapping to pin) */
39 /* gpio port data mirror register (bit mapping to pin) */
41 /* gpio port output type register (bit mapping to pin) */
130 [IT8XXX2_IRQ_WU20] = {BIT(0), 2, BIT(0)},
131 [IT8XXX2_IRQ_WU21] = {BIT(1), 2, BIT(1)},
132 [IT8XXX2_IRQ_WU22] = {BIT(4), 2, BIT(2)},
133 [IT8XXX2_IRQ_WU23] = {BIT(6), 2, BIT(3)},
134 [IT8XXX2_IRQ_WU24] = {BIT(2), 2, BIT(4)},
135 [IT8XXX2_IRQ_WU40] = {BIT(5), 4, BIT(0)},
136 [IT8XXX2_IRQ_WU45] = {BIT(6), 4, BIT(5)},
[all …]
/Zephyr-latest/drivers/sensor/ams/tmd2620/
Dtmd2620.h15 #define TMD2620_ENABLE_WEN BIT(3)
16 #define TMD2620_ENABLE_PEN BIT(2)
17 #define TMD2620_ENABLE_PON BIT(0)
28 * If the WLONG bit is set:
57 #define TMD2620_PERS_PPERS (BIT(4) | BIT(5) | BIT(6) | BIT(7))
60 #define TMD2620_CFG0_WLONG BIT(2)
65 #define TMD2620_PCFG0_PPULSE_LEN_8US BIT(6)
66 #define TMD2620_PCFG0_PPULSE_LEN_16US BIT(7)
67 #define TMD2620_PCFG0_PPULSE_LEN_32US (BIT(6) | BIT(7))
70 #define TMD2620_PCFG0_PPULSE (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5))
[all …]
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v2.h38 #define SSCR0_ECS BIT(6)
39 #define SSCR0_SSE BIT(7)
42 #define SSCR0_EDSS BIT(20)
43 #define SSCR0_NCS BIT(21)
44 #define SSCR0_RIM BIT(22)
45 #define SSCR0_TIM BIT(23)
48 #define SSCR0_ACS BIT(30)
49 #define SSCR0_MOD BIT(31)
52 #define SSCR1_RIE BIT(0)
53 #define SSCR1_TIE BIT(1)
[all …]
Dssp_regs_v1.h37 #define SSCR0_ECS BIT(6)
38 #define SSCR0_SSE BIT(7)
41 #define SSCR0_EDSS BIT(20)
42 #define SSCR0_NCS BIT(21)
43 #define SSCR0_RIM BIT(22)
44 #define SSCR0_TIM BIT(23)
47 #define SSCR0_ACS BIT(30)
48 #define SSCR0_MOD BIT(31)
51 #define SSCR1_RIE BIT(0)
52 #define SSCR1_TIE BIT(1)
[all …]
/Zephyr-latest/drivers/serial/
Duart_rzt2m.h36 #define CCR0_MASK_RE BIT(0)
37 #define CCR0_MASK_TE BIT(4)
38 #define CCR0_MASK_DCME BIT(9)
39 #define CCR0_MASK_IDSEL BIT(10)
40 #define CCR0_MASK_RIE BIT(16)
41 #define CCR0_MASK_TIE BIT(20)
42 #define CCR0_MASK_TEIE BIT(21)
43 #define CCR0_MASK_SSE BIT(24)
45 #define CCR1_MASK_CTSE BIT(0)
46 #define CCR1_MASK_SPB2DT BIT(4)
[all …]
/Zephyr-latest/drivers/sensor/apds9253/
Dapds9253.h15 #define APDS9253_MAIN_CTRL_SAI_LS BIT(5)
16 #define APDS9253_MAIN_CTRL_SW_RESET BIT(4)
17 #define APDS9253_MAIN_CTRL_RGB_MODE BIT(2)
18 #define APDS9253_MAIN_CTRL_LS_EN BIT(1)
23 #define APDS9253_LS_MEAS_RATE_RES_19BIT_200MS BIT(4)
24 #define APDS9253_LS_MEAS_RATE_RES_18BIT_100MS BIT(5) /* default */
25 #define APDS9253_LS_MEAS_RATE_RES_17BIT_50MS (BIT(5) | BIT(4))
26 #define APDS9253_LS_MEAS_RATE_RES_16BIT_25MS BIT(6)
27 #define APDS9253_LS_MEAS_RATE_RES_13_3MS (BIT(6) | BIT(4))
29 #define APDS9253_LS_MEAS_RATE_MES_2000MS (BIT(2) | BIT(1) | BIT(0))
[all …]
/Zephyr-latest/drivers/usb_c/ppc/
Dnxp_nx20p3483_priv.h18 /** Bit mask for vendor id */
20 /** Bit mask for version id */
25 /** Bit mask for device mode */
41 /** Bit field for source path selection. If set, HV source path is selected, 5V otherwise. */
42 #define NX20P3483_REG_SWITCH_CTRL_SRC BIT(7)
46 /** Bit field for 5V source switch enabled */
47 #define NX20P3483_REG_SWITCH_STATUS_5VSRC BIT(2)
48 /** Bit field for HV source switch enabled */
49 #define NX20P3483_REG_SWITCH_STATUS_HVSRC BIT(1)
50 /** Bit field for HV sink switch enabled */
[all …]

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