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/Zephyr-latest/dts/bindings/led_strip/
Dworldsemi,ws2812-rpi_pico-pio.yaml2 # SPDX-License-Identifier: Apache-2.0
7 compatible: "worldsemi,ws2812-rpi_pico-pio"
9 include: pinctrl-device.yaml
12 bit-waveform:
15 This property defines the waveform for sending 1-bit data.
19 The T1 is equal to (T1H-T0H) or (T0L-T1L) in the datasheet.
21 Code-0
22 +------+ +---
26 ---+ +-----------------+
28 Code-1
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Dws2812.yaml4 # SPDX-License-Identifier: Apache-2.0
13 https://wp.josh.com/2014/05/13/ws2812-neopixels-are-not-so-finicky-once-you-get-to-know-them/
15 A 0 bit's pulse width is between 200 and 500 ns. A 1 bit's is
19 MOSI line. Use the worldsemi,ws2812-spi.yaml or
20 worldsemi,ws2812-gpio.yaml bindings instead of this file after
26 For the control signal (waveform) each bit is described with a 1.2 us pulse:
28 0 bit: 300 ns high and 900 ns low.
29 1 bit: 900 ns high and 300 ns low.
31 There is a +/- 80 ns tolerance for each timing.
33 The latch/reset delay is 250 us and it must be set using the reset-delay
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/Zephyr-latest/samples/drivers/led/led_strip/
Df070rb-bindings.h4 * SPDX-License-Identifier: Apache-2.0
13 * Each bit of the control signal (waveform) is described with a 1.2 us pulse:
14 * 0 bit: 300 ns high and 900 ns low.
15 * 1 bit: 900 ns high and 300 ns low.
17 * At 6 MHz, one bit represents 166.666 ns.
18 * 1200 ns -> 7.2 bits
19 * 300 ns -> 1.8 bits
20 * 900 ns -> 5.4 bits
/Zephyr-latest/boards/shields/adafruit_neopixel_grid_bff/boards/
Dadafruit_qt_py_rp2040.overlay3 * SPDX-License-Identifier: Apache-2.0
6 #include <dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
19 bff-ws2812 {
20 compatible = "worldsemi,ws2812-rpi_pico-pio";
22 pinctrl-0 = <&pinctrl_bff_ws2812>;
23 pinctrl-names = "default";
24 bit-waveform = <3>, <3>, <4>;
29 chain-length = <25>;
30 color-mapping = <LED_COLOR_ID_GREEN
33 reset-delay = <280>;
/Zephyr-latest/boards/adafruit/kb2040/
Dadafruit_kb2040.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
11 #include "adafruit_kb2040-pinctrl.dtsi"
14 #include <zephyr/dt-bindings/led/led.h>
20 zephyr,flash-controller = &ssi;
22 zephyr,shell-uart = &uart0;
23 zephyr,code-partition = &code_partition;
28 led-strip = &ws2812;
36 compatible = "fixed-partitions";
37 #address-cells = <1>;
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/Zephyr-latest/boards/sparkfun/pro_micro_rp2040/
Dsparkfun_pro_micro_rp2040.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "sparkfun_pro_micro_rp2040-pinctrl.dtsi"
13 #include <zephyr/dt-bindings/led/led.h>
19 zephyr,flash-controller = &ssi;
21 zephyr,code-partition = &code_partition;
26 led-strip = &ws2812;
37 compatible = "fixed-partitions";
38 #address-cells = <1>;
39 #size-cells = <1>;
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/Zephyr-latest/boards/waveshare/rp2040_zero/
Drp2040_zero.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "rp2040_zero-pinctrl.dtsi"
12 #include <zephyr/dt-bindings/led/led.h>
17 zephyr,flash-controller = &ssi;
19 zephyr,shell-uart = &uart0;
20 zephyr,code-partition = &code_partition;
26 led-strip = &ws2812;
34 compatible = "fixed-partitions";
35 #address-cells = <1>;
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/Zephyr-latest/drivers/clock_control/
Dclock_control_mchp_xec.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
30 * 32KHz period counter minimum for pass/fail: 16-bit
31 * 32KHz period counter maximum for pass/fail: 16-bit
32 * 32KHz duty cycle variation max for pass/fail: 16-bit
33 * 32KHz valid count minimum: 8-bit
47 #define CLK32K_FLAG_CRYSTAL_SE BIT(0)
48 #define CLK32K_FLAG_PIN_FB_CRYSTAL BIT(1)
99 uint32_t RSVD4[(0x00c0 - 0x0094) / 4];
116 #define XEC_CC_PCR_OSC_ID_PLL_LOCK BIT(8)
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/Zephyr-latest/boards/adafruit/qt_py_rp2040/
Dadafruit_qt_py_rp2040.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
11 #include "adafruit_qt_py_rp2040-pinctrl.dtsi"
14 #include <zephyr/dt-bindings/led/led.h>
20 zephyr,flash-controller = &ssi;
22 zephyr,shell-uart = &uart1;
23 zephyr,code-partition = &code_partition;
28 led-strip = &ws2812;
36 compatible = "fixed-partitions";
37 #address-cells = <1>;
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/Zephyr-latest/boards/seeed/xiao_rp2040/
Dxiao_rp2040.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
11 #include "xiao_rp2040-pinctrl.dtsi"
14 #include <zephyr/dt-bindings/led/led.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
21 zephyr,flash-controller = &ssi;
23 zephyr,shell-uart = &uart0;
24 zephyr,code-partition = &code_partition;
29 led-strip = &ws2812;
30 pwm-led0 = &pwm_led0;
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/Zephyr-latest/drivers/i2c/
Di2c_sam_twihs.c5 * SPDX-License-Identifier: Apache-2.0
13 * Only I2C Master Mode with 7 bit addressing is currently supported.
32 #include "i2c-priv.h"
78 /* From the datasheet "TWIHS Clock Waveform Generator Register" in i2c_clk_set()
82 cl_div = ((SOC_ATMEL_SAM_MCK_FREQ_HZ / (speed * 2U)) - 3) in i2c_clk_set()
94 return -EIO; in i2c_clk_set()
98 twihs->TWIHS_CWGR = TWIHS_CWGR_CLDIV(cl_div) | TWIHS_CWGR_CHDIV(cl_div) in i2c_clk_set()
106 const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config; in i2c_sam_twihs_configure()
107 Twihs *const twihs = dev_cfg->regs; in i2c_sam_twihs_configure()
113 return -EIO; in i2c_sam_twihs_configure()
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Di2c_sam_twi.c5 * SPDX-License-Identifier: Apache-2.0
14 * - Only I2C Master Mode with 7 bit addressing is currently supported.
15 * - No reentrancy support.
34 #include "i2c-priv.h"
79 /* From the datasheet "TWI Clock Waveform Generator Register" in i2c_clk_set()
83 cl_div = ((SOC_ATMEL_SAM_MCK_FREQ_HZ / (speed * 2U)) - 4) in i2c_clk_set()
95 return -EIO; in i2c_clk_set()
99 twi->TWI_CWGR = TWI_CWGR_CLDIV(cl_div) | TWI_CWGR_CHDIV(cl_div) in i2c_clk_set()
107 const struct i2c_sam_twi_dev_cfg *const dev_cfg = dev->config; in i2c_sam_twi_configure()
108 struct i2c_sam_twi_dev_data *const dev_data = dev->data; in i2c_sam_twi_configure()
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Di2c_sam_twihs_rtio.c6 * SPDX-License-Identifier: Apache-2.0
14 * Only I2C Controller Mode with 7 bit addressing is currently supported.
33 #include "i2c-priv.h"
66 /* From the datasheet "TWIHS Clock Waveform Generator Register" in i2c_clk_set()
70 cl_div = ((SOC_ATMEL_SAM_MCK_FREQ_HZ / (speed * 2U)) - 3) in i2c_clk_set()
82 return -EIO; in i2c_clk_set()
86 twihs->TWIHS_CWGR = TWIHS_CWGR_CLDIV(cl_div) | TWIHS_CWGR_CHDIV(cl_div) in i2c_clk_set()
94 const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config; in i2c_sam_twihs_configure()
95 Twihs *const twihs = dev_cfg->regs; in i2c_sam_twihs_configure()
101 return -EIO; in i2c_sam_twihs_configure()
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Di2c_bitbang.c4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Software driven 'bit-banging' library for I2C
13 * the Standard-mode and Fast-mode speeds and doesn't support optional
14 * protocol feature like 10-bit addresses or clock stretching.
17 * https://www.nxp.com/docs/en/user-guide/UM10204.pdf
26 * Indexes into delay table for each part of I2C timing waveform we are
46 return -ENOTSUP; in i2c_bitbang_configure()
52 context->delays[T_LOW] = NS_TO_SYS_CLOCK_HW_CYCLES(4700); in i2c_bitbang_configure()
53 context->delays[T_HIGH] = NS_TO_SYS_CLOCK_HW_CYCLES(4000); in i2c_bitbang_configure()
56 context->delays[T_LOW] = NS_TO_SYS_CLOCK_HW_CYCLES(1300); in i2c_bitbang_configure()
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Di2c_sam4l_twim.c3 * Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
5 * SPDX-License-Identifier: Apache-2.0
13 * I2C Master Mode with 7/10 bit addressing is currently supported.
33 #include "i2c-priv.h"
109 const struct i2c_sam_twim_dev_cfg *const cfg = dev->config; in i2c_clk_set()
110 Twim *const twim = cfg->regs; in i2c_clk_set()
126 return -EIO; in i2c_clk_set()
130 TWIM_HSCWGR_HIGH(f_prescaled - in i2c_clk_set()
137 * Set clock waveform generator register in i2c_clk_set()
140 twim->HSCWGR = cwgr_reg_val; in i2c_clk_set()
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/Zephyr-latest/samples/drivers/clock_control_xec/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
12 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
24 uint32_t r = pcr->PWR_RST_STS; in pcr_clock_regs()
28 LOG_INF("PCR Power Reset Status register(bit[10] is 32K_ACTIVE) = 0x%x", r); in pcr_clock_regs()
30 r = pcr->OSC_ID; in pcr_clock_regs()
31 LOG_INF("PCR Oscillator ID register(bit[8]=PLL Lock) = 0x%x", r); in pcr_clock_regs()
33 r = pcr->PROC_CLK_CTRL; in pcr_clock_regs()
36 r = pcr->SLOW_CLK_CTRL; in pcr_clock_regs()
43 uint32_t cken = vbr->CLK32_EN; in vbat_clock_regs()
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/Zephyr-latest/doc/releases/
Drelease-notes-3.2.rst13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
56 This definition can be used by third-party code to compile code conditional
58 Therefore, any third-party code integrated using the Zephyr build system will
91 changed from ``-ENETDOWN`` to ``-ENETUNREACH``. A return value of ``-ENETDOWN`` now indicates
129 * Removed support for configuring the CAN-FD maximum DLC value via Kconfig
156 valid for specific bindings to specify like :dtcompatible:`gpio-leds` and
157 :dtcompatible:`fixed-partitions`.
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