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/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/
Dpmc_interface.h2 * SPDX-License-Identifier: Apache-2.0
18 * The requesting agent will write the PMC command op-code into this field.
24 * this field.
29 * Some commands require additional information which is passed into this 8 bit field.
34 * Some commands require additional information which is passed into this 8 bit field.
39 * Some commands require additional information which is passed into this 4 bit field.
49 * busy - The run/busy bit can only be set by the requesting agent and can only be cleared by the
50 * responding agent. When this bit is set it will prompt the PMC to execute the command placed in
52 * code has been written back into the COMMAND field and any data requested has been written into
53 * the DATA field.
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/Zephyr-Core-3.5.0/soc/arm/nuvoton_npcx/common/reg/
Dreg_access.h4 * SPDX-License-Identifier: Apache-2.0
11 * NPCX register bit/field access operations
13 #define IS_BIT_SET(reg, bit) (((reg >> bit) & (0x1)) != 0) argument
17 #define FIELD_POS(field) GET_POS_##field argument
18 #define FIELD_SIZE(field) GET_SIZE_##field argument
20 #define GET_FIELD(reg, field) \ argument
21 _GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field))
22 #define _GET_FIELD_(reg, f_pos, f_size) (((reg)>>(f_pos)) & ((1<<(f_size))-1))
24 #define SET_FIELD(reg, field, value) \ argument
25 _SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value)
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Dreg_def.h4 * SPDX-License-Identifier: Apache-2.0
20 * must meet the alignment requirement of cortex-m4.
44 __ASSERT(reg == val, "16-bit reg access failed!"); \
50 __ASSERT(reg == val, "32-bit reg access failed!"); \
87 /* 0x102: High-Frequency Reference Divisor I */
89 /* 0x104: High-Frequency Reference Divisor F */
124 /* 0x008 - 0D: Power-Down Control 1 - 6 */
127 /* 0x020 - 21: Power-Down Control 1 - 2 */
130 /* 0x024: Power-Down Control 7 */
134 /* PMC internal inline functions for multi-registers */
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/Zephyr-Core-3.5.0/include/zephyr/drivers/pinctrl/
Dpinctrl_soc_gd32_common.h4 * SPDX-License-Identifier: Apache-2.0
19 #include <dt-bindings/pinctrl/gd32-af.h>
21 #include <dt-bindings/pinctrl/gd32-afio.h>
33 * - 0-12: GD32_PINMUX_AF bit field.
34 * - 13-25: Reserved.
35 * - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
38 * - 0-19: GD32_PINMUX_AFIO bit field.
39 * - 20-25: Reserved.
40 * - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
79 /** No pull-up/down */
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Dpinctrl_soc_sam_common.h4 * SPDX-License-Identifier: Apache-2.0
17 #include <dt-bindings/pinctrl/atmel_sam_pinctrl.h>
28 * - 0-15: SAM pinmux bit field (@ref SAM_PINMUX).
29 * - 16-21: Pin flags bit field (@ref SAM_PINFLAGS).
30 * - 22-31: Reserved.
102 * @param pincfg pinctrl_soc_pin_t bit field value.
103 * @param pos attribute/flags bit position (@ref SAM_PINFLAGS).
/Zephyr-Core-3.5.0/drivers/spi/
Dspi_andes_atcspi200.h4 * SPDX-License-Identifier: Apache-2.0
31 #define SPI_BASE (((const struct spi_atcspi200_cfg *)(dev)->config)->base)
43 /* Field mask of SPI transfer format register */
46 #define TFMAT_CPHA_MSK BIT(0)
47 #define TFMAT_CPOL_MSK BIT(1)
48 #define TFMAT_SLVMODE_MSK BIT(2)
49 #define TFMAT_LSB_MSK BIT(3)
50 #define TFMAT_DATA_MERGE_MSK BIT(7)
54 /* Field mask of SPI transfer control register */
67 /* Field mask of SPI interrupt enable register */
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/Zephyr-Core-3.5.0/drivers/flash/
Dflash_andes_qspi.h4 * SPDX-License-Identifier: Apache-2.0
26 #define FLASH_ANDES_WIP_BIT BIT(0) /* Write in progress */
27 #define FLASH_ANDES_WEL_BIT BIT(1) /* Write enable latch */
28 #define FLASH_ANDES_QE_BIT BIT(6)
42 /* Field mask of SPI transfer format register */
46 #define TFMAT_SLVMODE_MSK BIT(2)
47 #define TFMAT_DATA_MERGE_MSK BIT(7)
50 /* Field mask of SPI transfer control register */
58 #define TCTRL_ADDR_FMT_MSK BIT(28)
59 #define TCTRL_ADDR_EN_MSK BIT(29)
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/Zephyr-Core-3.5.0/drivers/sensor/vl53l0x/
Dvl53l0x_platform.h1 /* vl53l0x_platform.h - Zephyr customization of ST vl53l0x library.
8 * SPDX-License-Identifier: Apache-2.0
29 /*!< user specific field */
30 uint8_t I2cDevAddr; /* i2c device address user specific field */
47 * @param field ST structure field name
48 * It maybe used and as real data "ref" not just as "get" for sub-structure item
49 * like PALDevDataGet(FilterData.field)[i]
52 #define PALDevDataGet(Dev, field) (Dev->Data.field) argument
55 * @brief Set ST private structure @a VL53L0X_DevData_t data field
57 * @param field ST structure field name
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/Zephyr-Core-3.5.0/soc/arm/nordic_nrf/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/pinctrl/nrf-pinctrl.h>
58 * @param pincfg Pin configuration bit field.
65 * @param pincfg Pin configuration bit field.
72 * @param pincfg Pin configuration bit field.
79 * @param pincfg Pin configuration bit field.
86 * @param pincfg Pin configuration bit field.
93 * @param pincfg Pin configuration bit field.
/Zephyr-Core-3.5.0/dts/bindings/mtd/
Dnxp,imx-flexspi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: [spi-device.yaml, "jedec,jesd216.yaml"]
9 cs-interval-unit:
13 - 1
14 - 256
17 CSINTERVALUNIT field in registers FLASHA1CR0 through FLASHB2CR0. The
18 default corresponds to the reset value of the register field.
20 cs-interval:
25 CSINTERVAL field in registers FLASHA1CR0 through FLASHB2CR0. The
26 default corresponds to the reset value of the register field.
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/Zephyr-Core-3.5.0/soc/arm/silabs_exx32/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
19 #include <zephyr/dt-bindings/pinctrl/gecko-pinctrl-s1.h>
21 #include <zephyr/dt-bindings/pinctrl/gecko-pinctrl.h>
57 * @param pincfg Pin configuration bit field.
64 * @param pincfg port configuration bit field.
71 * @param pincfg pin configuration bit field.
78 * @param pincfg Loc configuration bit field.
85 * @param pincfg speed configuration bit field.
/Zephyr-Core-3.5.0/tests/drivers/pinctrl/api/src/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
19 * @name Test pin configuration bit field positions and masks.
27 /** Position of the pull field. */
29 /** Mask of the pull field. */
31 /** Position of the pin field. */
33 /** Mask for the pin field. */
39 * @name Test pinctrl pull-up/down.
43 /** Pull-up disabled. */
45 /** Pull-down enabled. */
47 /** Pull-up enabled. */
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/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/
Dgecko-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole GECKO_pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 23..16: Reserved.
15 * - 15..8: Port for UART_RX/UART_TX functions.
16 * - 7..0: Pin number for UART_RX/UART_TX functions.
17 * - 15..8: Reserved for UART_LOC function.
18 * - 7..0: Loc for UART_LOC function.
22 * @name GECKO_pin configuration bit field positions and masks.
26 /** Position of the function field. */
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Dgecko-pinctrl-s1.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole GECKO_pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 23..16: Reserved.
15 * - 15..8: Port for UART_RX/UART_TX functions.
16 * - 7..0: Pin number for UART_RX/UART_TX functions.
17 * - 15..8: Reserved for UART_LOC function.
18 * - 7..0: Loc for UART_LOC function.
22 * @name GECKO_pin configuration bit field positions and masks.
26 /** Position of the function field. */
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Dstm32f1-afio.h4 * SPDX-License-Identifier: Apache-2.0
20 * @brief STM32F1 Remap configuration bit field.
22 * - reg (0/1) [ 0 : 0 ]
23 * - shift (0..31) [ 1 : 5 ]
24 * - mask (0x1, 0x3) [ 6 : 7 ]
25 * - val (0..3) [ 8 : 9 ]
29 * @param mask Mask for the AFIO_MAPRx field.
42 * Obtain register field from remap configuration.
44 * @param remap Remap bit field value.
50 * Obtain position field from remap configuration.
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/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/gpio/
Dnordic-npm1300-gpio.h4 * SPDX-License-Identifier: Apache-2.0
10 * @brief nPM1300-specific GPIO Flags
11 * @defgroup gpio_interface_npm1300 nPM1300-specific GPIO Flags
16 * - Bit 8: Drive strength (0=1mA, 1=6mA)
17 * - Bit 9: Debounce (0=OFF, 1=ON)
18 * - Bit 10: Watchdog reset (0=OFF, 1=ON)
19 * - Bit 11: Power loss warning (0=OFF, 1=ON)
32 /** Drive mode field mask */
50 /** Debounce field mask */
68 /** watchdog reset field mask */
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Dnordic-npm6001-gpio.h4 * SPDX-License-Identifier: Apache-2.0
10 * @brief nPM6001-specific GPIO Flags
11 * @defgroup gpio_interface_npm6001 nPM6001-specific GPIO Flags
16 * - Bit 8: Drive strength (0=NORMAL, 1=HIGH)
17 * - Bit 9: Input type (0=SCHMITT, 1=CMOS)
30 /** Drive mode field mask */
48 /** Input type field mask */
/Zephyr-Core-3.5.0/include/zephyr/drivers/rtc/
Dmaxim_ds3231.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Real-time clock control based on the DS3231 counter API.
12 * DS3231](https://www.maximintegrated.com/en/products/analog/real-time-clocks/DS3231.html)
13 * is a high-precision real-time clock with temperature-compensated
28 * functionality exposed by this header to access the real-time-clock
46 /** @brief Bit in ctrl or ctrl_stat associated with alarm 1. */
47 #define MAXIM_DS3231_ALARM1 BIT(0)
49 /** @brief Bit in ctrl or ctrl_stat associated with alarm 2. */
50 #define MAXIM_DS3231_ALARM2 BIT(1)
57 /** @brief ctrl bit for alarm 1 interrupt enable. */
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/Zephyr-Core-3.5.0/drivers/sensor/fdc2x1x/
Dfdc2x1x.h4 * SPDX-License-Identifier: Apache-2.0
65 /* CLOCK_DIVIDERS_CHX Field Descriptions */
73 /* STATUS Field Descriptions */
85 #define FDC2X1X_ERROR_CONFIG_WD_ERR2OUT_MSK BIT(13)
88 #define FDC2X1X_ERROR_CONFIG_AH_WARN2OUT_MSK BIT(12)
91 #define FDC2X1X_ERROR_CONFIG_AL_WARN2OUT_MSK BIT(11)
94 #define FDC2X1X_ERROR_CONFIG_WD_ERR2INT_MSK BIT(5)
97 #define FDC2X1X_ERROR_CONFIG_DRDY_2INT_MSK BIT(0)
101 /* CONFIG Field Descriptions */
105 #define FDC2X1X_CFG_SLEEP_SET_EN_MSK BIT(13)
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/Zephyr-Core-3.5.0/drivers/dma/
Ddma_iproc_pax_v1.h4 * SPDX-License-Identifier: Apache-2.0
19 #define RM_COMM_CONTROL_CONFIG_DONE BIT(2)
21 #define RM_COMM_CONTROL_LINE_INTR_EN BIT(4)
23 #define RM_COMM_CONTROL_AE_TIMEOUT_EN BIT(5)
43 /* Bits 0:1 ignored by PAX DMA, i.e. 4-byte address alignment */
51 * Per-ring memory, with 8K & 4K alignment
61 /* RM header desc field */
75 /* dma desc header field */
84 /* dma desc AXI addr field */
91 /* dma desc PCI addr field */
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Ddma_iproc_pax_v2.h4 * SPDX-License-Identifier: Apache-2.0
23 #define RM_COMM_CONTROL_CONFIG_DONE BIT(2)
24 #define RM_COMM_CONTROL_LINE_INTR_EN BIT(4)
25 #define RM_COMM_CONTROL_AE_TIMEOUT_EN BIT(5)
58 * Per-ring memory, with 8K & 4K alignment
68 /* RM header desc field */
85 /* pcie desc field */
93 /* src/dst desc field */
104 uint64_t toggle : 1; /*Toggle Bit:59*/
/Zephyr-Core-3.5.0/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/
Dradio.h5 * SPDX-License-Identifier: Apache-2.0
9 /* PDU type, 2 bit field*/
16 /* PHY type, three bit field */
20 #define RADIO_PKT_CONF_PHY_1M (BIT(0U))
21 #define RADIO_PKT_CONF_PHY_2M (BIT(1U))
22 #define RADIO_PKT_CONF_PHY_CODED (BIT(2U))
23 /* CTE enabled, 1 bit field */
29 /* Macro to define length of the BLE packet length field in bits */
33 /* Macro to define length of the BLE packet S1 field in bits */
48 /* Helper macro to get CTE enable field value from radio packet configuration bitfield */
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/common/
Dsoc_gpio.h2 * Copyright (c) 2016-2017 Piotr Mienkowski
4 * SPDX-License-Identifier: Apache-2.0
37 /* Bit field: SOC_GPIO_IN_FILTER */
46 /* Bit field: SOC_GPIO_INT_TRIG */
59 /* Bit field: SOC_GPIO_FUNC */
86 uint32_t mask; /** pin(s) bit mask */
101 * - configure pin(s) as input with debounce filter enabled.
102 * - connect pin(s) to a peripheral B and enable pull-up.
103 * - configure pin(s) as open drain output.
111 * a pull-up and user wants to read pin's input value it is necessary
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/Zephyr-Core-3.5.0/drivers/watchdog/
Dwdt_intel_adsp.h1 /* SPDX-License-Identifier: Apache-2.0 */
31 * FW write 76h as the code to set the PAUSED bit. Other value are ignored and has no effect.
41 * field. Clear when FW writes a 1 to the bit.
43 #define DSPCxWDTCS_PAUSED BIT(8)
50 * watch dog timer. Clear when DSPCCTL.CPA = 0. Set when FW writes a 1 to the bit.
52 #define DSPCxWDTCS_STORE BIT(9)
69 * This field contains the offset to the IP.
77 * This field indicates the version of the IP.
137 * watch dog timer. Clear when DSPCCTL.CPA = 0. Set when FW writes a 1 to the bit.
139 #define DSPCxWDTCS_STORE BIT(9)
/Zephyr-Core-3.5.0/drivers/ieee802154/
Dieee802154_dw1000_regs.h4 * SPDX-License-Identifier: Apache-2.0
7 * https://github.com/Decawave/mynewt-dw1000-core.git
14 * Copyright (C) 2017-2018, Decawave Limited, All Rights Reserved
24 * http://www.apache.org/licenses/LICENSE-2.0
73 /* Frame Filtering Enable. This bit enables the frame filtering functionality */
75 /* Frame Filtering Behave as a Co-ordinator */
87 /* Frame Filtering Allow frames with frame type field of 4, (binary 100) */
89 /* Frame Filtering Allow frames with frame type field of 5, (binary 101) */
117 * Receiver Auto-Re-enable.
118 * This bit is used to cause the receiver to re-enable automatically
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