Searched +full:bias +full:- +full:push +full:- +full:pull (Results 1 – 25 of 29) sorted by relevance
12
| /Zephyr-Core-3.5.0/boards/arm/apollo4p_evb/ |
| D | apollo4p_evb-pinctrl.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h>
16 input-enable;
22 drive-open-drain;
23 drive-strength = "0.5";
24 bias-pull-up;
30 drive-open-drain;
31 drive-strength = "0.5";
32 bias-pull-up;
38 drive-open-drain;
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/apollo4p_blue_kxr_evb/ |
| D | apollo4p_blue_kxr_evb-pinctrl.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h>
16 input-enable;
22 drive-open-drain;
23 drive-strength = "0.5";
24 bias-pull-up;
30 drive-open-drain;
31 drive-strength = "0.5";
32 bias-pull-up;
38 drive-open-drain;
[all …]
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| /Zephyr-Core-3.5.0/dts/bindings/pinctrl/ |
| D | infineon,cat1-pinctrl.yaml | 4 # SPDX-License-Identifier: Apache-2.0
11 UART0 RX to a particular port/pin and enable the pull-up resistor on that
22 'bias-pull-up' property. Here is a list of the supported standard pin
24 * bias-high-impedance
25 * bias-pull-up
26 * bias-pull-down
27 * drive-open-drain
28 * drive-open-source
29 * drive-push-pull (strong)
30 * input-enable (input-buffer)
[all …]
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| D | ti,cc32xx-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route UART0 RX to pin 55 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
39 /* both pin 57 and 62 have pull-up enabled */
40 bias-pull-up;
53 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
56 - drive-push-pull: Push-pull drive mode (default, not required).
57 - drive-open-drain: Open-drain drive mode.
[all …]
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| D | microchip,xec-pinctrl.yaml | 3 # SPDX-License-Identifier: Apache-2.0
7 Based on pincfg-node.yaml binding.
23 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
26 - bias-disable: Disable pull-up/down (default behavior, not required).
27 - bias-pull-down: Enable pull-down resistor.
28 - bias-pull-up: Enable pull-up resistor.
29 - drive-push-pull: Output driver is push-pull (default, not required).
30 - drive-open-drain: Output driver is open-drain.
31 - output-high: Set output state high when pin configured.
32 - output-low: Set output state low when pin configured.
[all …]
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| D | gd,gd32-pinctrl-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 child-binding:
7 child-binding:
9 - name: pincfg-node.yaml
10 property-allowlist:
11 - drive-push-pull
12 - drive-open-drain
13 - bias-disable
14 - bias-pull-down
15 - bias-pull-up
[all …]
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| D | gd,gd32-pinctrl-af.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
39 /* both PA10 and PA12 have pull-up enabled */
40 bias-pull-up;
56 is used for low power states because it disconnects the pin pull-up/down
64 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
67 - drive-push-pull: Push-pull drive mode (default, not required).
[all …]
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| D | cypress,psoc6-pinctrl.yaml | 3 # SPDX-License-Identifier: Apache-2.0
6 Cypress PSoC-6 Pinctrl container node
8 The Cypress PSoC-6 pins implements following pin configuration option:
10 * bias-pull-up
11 * bias-pull-down
12 * drive-open-drain
13 * drive-open-source
14 * drive-push-pull (strong)
15 * input-enable (input-buffer)
20 compatible: "cypress,psoc6-pinctrl"
[all …]
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| D | st,stm32-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32-pinctrl"
20 remap-pa11:
25 remap-pa12:
30 remap-pa11-pa12:
35 child-binding:
40 - name: pincfg-node.yaml
[all …]
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| D | espressif,esp32-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 states are composed by groups of pre-defined pin muxing definitions and user
10 Each Zephyr-based application has its own set of pin muxing/pin configuration
11 requirements. The next steps use ESP-WROVER-KIT's I2C_0 to illustrate how one
15 Suppose an application running on top of the ESP-WROVER-KIT board, for some
18 you'll notice that the I2C_0 node is already assigned to a pre-defined state.
22 #include "esp_wrover_kit-pinctrl.dtsi"
26 pinctrl-0 = <&i2c0_default>;
27 pinctrl-names = "default";
31 From the above excerpt, the pincrl-0 property is assigned the 'i2c0_default'
[all …]
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| D | pincfg-node.yaml | 2 # SPDX-License-Identifier: Apache-2.0
16 https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
19 bias-disable:
21 description: disable any pin bias
23 bias-high-impedance:
25 description: high impedance mode ("third-state", "floating")
27 bias-bus-hold:
31 bias-pull-up:
33 description: enable pull-up resistor
35 bias-pull-down:
[all …]
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| D | gd,gd32-pinctrl-afio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f403z(k-i-g-e-c-b)xx-pinctrl.h>
39 /* both PA10 and PA12 have pull-up enabled */
40 bias-pull-up;
56 is used for low power states because it disconnects the pin pull-up/down
64 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
67 - drive-push-pull: Push-pull drive mode (default, not required). Only
[all …]
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| D | st,stm32f1-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32f1-pinctrl"
20 swj-cfg:
24 - "full"
25 - "no-njtrst"
26 - "jtag-disable"
27 - "disable"
[all …]
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| D | nxp,lpc-iocon-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
16 slew-rate = "standard";
24 IOCON_SLEW=<slew-rate selection>,
38 drive-open-drain: IOCON_OD=1
39 bias-pull-up: IOCON_MODE=2
40 bias-pull-down: IOCON_MODE=1
41 drive-push-pull: IOCON_MODE=3
44 IOCON_HYS- set by input-schmitt-enable
45 IOCON_S_MODE- set by nxp,digital-filter
46 IOCON_CLKDIV- set by nxp,filter-clock-div
[all …]
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| D | ite,it8xxx2-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined pins and functions for the SoC used by the board */
25 #include <dt-bindings/pinctrl/it8xxx2-pinctrl.h>
31 gpio-voltage = "1p8";
35 gpio-voltage = "1v8";
40 bias-pull-up;
51 To link pin configurations with a device, use a pinctrl-N property for some
54 #include "board-pinctrl.dtsi"
57 pinctrl-0 = <&uart1_rx_pb0_default &uart1_tx_pb1_default>;
[all …]
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| D | nxp,lpc11u6x-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 compatible: "nxp,lpc11u6x-pinctrl"
7 - name: base.yaml
8 - name: nxp,lpc-iocon-pinctrl.yaml
9 child-binding:
10 child-binding:
11 property-allowlist:
12 - pinmux
13 - nxp,invert
14 - nxp,analog-mode
[all …]
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| D | infineon,xmc4xxx-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
12 compatible = "infineon,xmc4xxx-uart";
13 pinctrl-0 = <&uart_tx_p0_1_u1c1 &uart_rx_p0_0_u1c1>;
14 pinctrl-names = "default";
15 input-src = "DX0D";
19 pinctrl-0 is the phandle that stores the pin settings for two pins: &uart_tx_p0_1_u1c1
20 and &uart_rx_p0_0_u1c1. These nodes are pre-defined and their naming convention is designed
24 The pre-defined nodes only set the alternate function of the output pin. The
27 to the inherited property-allowlist list from pincfg-node.yaml).
31 #include <zephyr/dt-bindings/pinctrl/xmc4xxx-pinctrl.h>
[all …]
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| D | ambiq,apollo4-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
19 /* You can put this in places like a board-pinctrl.dtsi file in
23 /* include pre-defined combinations for the SoC variant used by the board */
24 #include <dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h>
33 input-enable;
47 pins, such as the 'input-enable' property in group 2.
49 compatible: "ambiq,apollo4-pinctrl"
53 child-binding:
56 child-binding:
59 - name: pincfg-node.yaml
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/cy8cproto_062_4343w/ |
| D | cy8cproto_062_4343w-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
6 /* Configure pin control bias mode for uart2 pins */
8 drive-push-pull;
12 input-enable;
16 drive-push-pull;
20 input-enable;
23 /* Configure pin control bias mode for uart5 pins */
25 drive-push-pull;
29 input-enable;
|
| /Zephyr-Core-3.5.0/tests/drivers/w1/w1_api/boards/ |
| D | nucleo_g0b1re.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 * enable open-drain drive such that no external push-pull to
10 * open-drain converter is required. An external pull-up resistor
14 drive-open-drain;
15 bias-pull-up;
|
| /Zephyr-Core-3.5.0/tests/drivers/pinctrl/gd32/boards/ |
| D | gd32f450i_eval.overlay | 3 * SPDX-License-Identifier: Apache-2.0
8 compatible = "vnd,pinctrl-device";
9 pinctrl-0 = <&test_device_default>;
10 pinctrl-names = "default";
25 drive-push-pull;
29 drive-open-drain;
33 bias-disable;
37 bias-pull-up;
41 bias-pull-down;
45 slew-rate = "max-speed-2mhz";
[all …]
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| D | gd32f403z_eval.overlay | 3 * SPDX-License-Identifier: Apache-2.0
10 compatible = "vnd,pinctrl-device";
11 pinctrl-0 = <&test_device_default>;
12 pinctrl-names = "default";
32 drive-push-pull;
36 drive-open-drain;
40 bias-disable;
44 bias-pull-up;
48 bias-pull-down;
52 slew-rate = "max-speed-2mhz";
[all …]
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| /Zephyr-Core-3.5.0/tests/drivers/spi/spi_loopback/boards/ |
| D | cy8cproto_062_4343w.overlay | 2 compatible = "infineon,cat1-spi";
5 pinctrl-0 = <&p6_0_scb3_spi_m_mosi &p6_1_scb3_spi_m_miso &p6_2_scb3_spi_m_clk>;
6 pinctrl-names = "default";
7 cs-gpios = <&gpio_prt6 3 GPIO_ACTIVE_LOW>;
10 compatible = "test-spi-loopback-slow";
12 spi-max-frequency = <2000000>;
15 compatible = "test-spi-loopback-fast";
17 spi-max-frequency = <3000000>;
26 /* Configure pin control bias mode for SPI pins */
29 drive-push-pull;
[all …]
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| D | cy8cproto_063_ble.overlay | 2 /* Configure pin control bias mode for SPI pins (MASTER) */
5 drive-push-pull;
10 input-enable;
15 drive-push-pull;
20 compatible = "infineon,cat1-spi";
23 pinctrl-0 = <&p10_0_scb1_spi_m_mosi &p10_1_scb1_spi_m_miso &p10_2_scb1_spi_m_clk>;
24 pinctrl-names = "default";
25 cs-gpios = <&gpio_prt10 3 GPIO_ACTIVE_LOW>;
28 compatible = "test-spi-loopback-slow";
30 spi-max-frequency = <200000>;
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/cy8cproto_063_ble/ |
| D | cy8cproto_063_ble-pinctrl.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 /* Configure pin control bias mode for uart5 pins */
9 drive-push-pull;
13 input-enable;
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