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/Zephyr-latest/drivers/mm/
Dmm_drv_bank.c21 void sys_mm_drv_bank_init(struct sys_mm_drv_bank *bank, uint32_t bank_pages) in sys_mm_drv_bank_init() argument
23 bank->unmapped_pages = 0; in sys_mm_drv_bank_init()
24 bank->mapped_pages = bank_pages; in sys_mm_drv_bank_init()
25 bank->max_mapped_pages = bank_pages; in sys_mm_drv_bank_init()
28 uint32_t sys_mm_drv_bank_page_mapped(struct sys_mm_drv_bank *bank) in sys_mm_drv_bank_page_mapped() argument
30 bank->unmapped_pages--; in sys_mm_drv_bank_page_mapped()
31 bank->mapped_pages++; in sys_mm_drv_bank_page_mapped()
32 if (bank->mapped_pages > bank->max_mapped_pages) { in sys_mm_drv_bank_page_mapped()
33 bank->max_mapped_pages = bank->mapped_pages; in sys_mm_drv_bank_page_mapped()
35 return bank->mapped_pages; in sys_mm_drv_bank_page_mapped()
[all …]
/Zephyr-latest/include/zephyr/drivers/mm/
Dmm_drv_bank.h54 * @brief Initialize a memory bank's data structure
62 * @param[in,out] bank Pointer to the memory bank structure used for tracking
63 * @param[in] bank_pages Number of pages in the memory bank
65 void sys_mm_drv_bank_init(struct sys_mm_drv_bank *bank, uint32_t bank_pages);
68 * @brief Track the mapping of a page in the specified memory bank
71 * specified memory bank.
73 * @param[in,out] bank Pointer to the memory bank's data structure
75 * @return The number of pages mapped within the memory bank
77 uint32_t sys_mm_drv_bank_page_mapped(struct sys_mm_drv_bank *bank);
80 * @brief Track the unmapping of a page in the specified memory bank
[all …]
/Zephyr-latest/dts/bindings/gpio/
Dxlnx,ps-gpio.yaml19 * Bank 0: MIO pins [31:00]
20 * Bank 1: MIO pins [53:32] (total: 54 MIO pins)
21 * Bank 2: EMIO pins [31:00]
22 * Bank 3: EMIO pins [63:32] (total: 64 EMIO pins)
25 * Bank 0: MIO pins [25:00]
26 * Bank 1: MIO pins [51:26]
27 * Bank 2: MIO pins [77:52] (total: 78 MIO pins, 26 per bank)
28 * Bank 3: EMIO pins [31:00]
29 * Bank 4: EMIO pins [63:32]
30 * Bank 5: EMIO pins [95:64] (total: 96 EMIO pins)
Dxlnx,ps-gpio-bank.yaml7 Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller bank node.
10 a bank of the MIO/EMIO GPIO controller integrated in the Processor
13 compatible: "xlnx,ps-gpio-bank"
Dambiq,gpio.yaml13 devicetree and some child nodes which are compatible with "ambiq,gpio-bank"
36 compatible = "ambiq,gpio-bank";
45 compatible = "ambiq,gpio-bank";
54 compatible = "ambiq,gpio-bank";
63 compatible = "ambiq,gpio-bank";
73 provides the base register address 0x40010000. It has four "ambiq,gpio-bank"
Dambiq,gpio-bank.yaml5 description: Ambiq GPIO bank node
7 compatible: "ambiq,gpio-bank"
/Zephyr-latest/drivers/gpio/
Dgpio_xlnx_ps.c39 * bank's child device.
49 uint32_t bank; in gpio_xlnx_ps_init() local
56 /* Propagate the virtual base address to the bank devices */ in gpio_xlnx_ps_init()
57 for (bank = 0; bank < dev_conf->num_banks; bank++) { in gpio_xlnx_ps_init()
59 dev_conf->bank_devices[bank]->data; in gpio_xlnx_ps_init()
60 __ASSERT(bank_data != NULL, "%s bank %u data unresolved", dev->name, bank); in gpio_xlnx_ps_init()
74 * IRQ. The ISR iterates all associated MIO / EMIO GPIO pink bank
75 * child device instances and checks each bank's interrupt status.
76 * If any pending interrupt is detected within a GPIO pin bank,
77 * the callbacks registered for the respective bank are triggered
[all …]
Dgpio_xlnx_ps_bank.c3 * GPIO bank module
28 * @brief GPIO bank pin configuration function
30 * Configures an individual pin within a MIO / EMIO GPIO pin bank.
39 * @param dev Pointer to the GPIO bank's device.
40 * @param pin Index of the pin within the bank to be configured
116 * @brief Reads the current bit mask of the entire GPIO pin bank.
118 * Reads the current bit mask of the entire bank from the
121 * pins within the bank.
123 * @param dev Pointer to the GPIO bank's device.
125 * to which the current bit mask read from the bank's
[all …]
Dgpio_xlnx_ps_bank.h4 * Driver private data declarations, GPIO bank module
47 * This struct contains all data of a PS MIO / EMIO GPIO bank
50 * to the respective bank.
61 * This struct contains all data of a PS MIO / EMIO GPIO bank
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dasm_memory_management.h17 /* Retrieve the LPSRAM bank count from the ACE_L2MCAP register */
20 /* Extract the 4-bit bank count field starting from bit 8 */
28 /* Issue the power down command to the current LPSRAM bank */
36 /* Move to the next LPSRAM bank control register */
38 addi \au, \au, -1 /* Decrement bank count */
43 /* Read the HPSRAM bank count from ACE_L2MCAP register */
46 extui \au, \au, 0, 8 /* Bank count is in the lower 8 bits */
59 addi \az, \az, DT_REG_SIZE(DT_NODELABEL(hsbpm)) /* Move to next bank control register */
60 addi \au, \au, -1 /* Decrement bank count */
/Zephyr-latest/dts/bindings/flash_controller/
Dst,stm32wb-flash-controller.yaml8 single-bank:
10 description: dual-bank mode not enabled (page erase 4096k)
12 dual-bank:
14 description: dual-bank mode enabled (page erase 2048k)
Dgd,gd32-flash-controller.yaml7 GD32 FMC v1: its flash memory has 1 bank, page size is equal in the bank,
10 GD32 FMC v2: its flash memory has 2 banks. Page size equal within the same bank but
/Zephyr-latest/drivers/ethernet/
Deth_smsc91x_priv.h11 /* All Banks, Offset 0xe: Bank Select Register */
13 #define BSR_BANK_MASK GENMASK(2, 0) /* Which bank is currently selected */
17 /* Bank 0, Offset 0x0: Transmit Control Register */
22 /* Bank 0, Offset 0x02: EPH status register */
26 /* Bank 0, Offset 0x4: Receive Control Register */
40 /* Bank 0, Offset 0x8: Memory information register */
45 /* bank 0, offset 0xa: receive/phy control register */
60 /* Bank 1, Offset 0x0: Configuration Register */
64 /* Bank 1, Offset 0x2: Base Address Register */
67 /* Bank 1, Offsets 0x4: Individual Address Registers */
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-rcar-common.h13 * Each IPSR bank can hold 8 cellules of 4 bits coded function.
15 * @param bank the IPSR register bank.
22 * IPSR bank [ 10 : 14 ]
25 #define IPSR(bank, shift, func) (((bank) << 10U) | ((shift) << 4U) | (func)) argument
33 * @param bank the GPIO bank
34 * @param pin the pin within the GPIO bank (0..31)
36 #define RCAR_GP_PIN(bank, pin) (((bank) * 32U) + (pin)) argument
49 #define IPnSR(bank, reg, shift, func) \ argument
50 IPSR(((reg) << 5U) | (bank), shift, func)
/Zephyr-latest/dts/bindings/memory-controllers/
Dnxp,flexram.yaml30 flexram,bank-size:
34 Size of each RAM bank in KB
36 flexram,bank-spec:
39 Custom mapping of runtime RAM bank partitions. If this
Dst,stm32-fmc-sdram.yaml14 defined as child nodes of the FMC SDRAM node. You can either have bank 1 (@0),
15 bank 2 (@1) or both. You can enable the FMC SDRAM controller in your board
30 bank@0 {
44 bank@1 {
72 It is important to use sdram1 and sdram2 node labels for bank 1 and bank 2
73 respectively. Memory addresses are 0xc0000000 and 0xd0000000 for bank 1 and
74 bank 2 respectively.
116 description: SDRAM bank.
/Zephyr-latest/tests/drivers/mm/sys_mm_drv_bank/src/
Dmain.c46 test_stats("MM Bank Init Error", &stats, &expected); in ZTEST()
58 test_stats("MM Bank Init Error", &stats, &expected); in ZTEST()
76 test_stats("MM Bank Mapped Error", &stats, &expected); in ZTEST()
88 test_stats("MM Bank Unmapped Error", &stats, &expected); in ZTEST()
100 test_stats("MM Bank 1st Max Mapped Error", &stats, &expected); in ZTEST()
110 test_stats("MM Bank 2nd Max Mapped Error", &stats, &expected); in ZTEST()
116 "MM Bank Reset Max Error: unmapped = %u, not %u\n", in ZTEST()
122 test_stats("MM Bank Reset Max Error", &stats, &expected); in ZTEST()
129 test_stats("MM Bank Reset Max Error", &stats, &expected); in ZTEST()
/Zephyr-latest/arch/arc/core/mpu/
Darc_mpu_v6_internal.h63 * This internal function select a MPU bank
65 static inline void _bank_select(uint32_t bank) in _bank_select() argument
70 z_arc_v2_aux_reg_write(_ARC_V2_MPU_EN, val | bank); in _bank_select()
78 uint32_t bank = index / ARC_FEATURE_MPU_BANK_SIZE; in _region_init() local
107 _bank_select(bank); in _region_init()
150 uint32_t bank = r_index / ARC_FEATURE_MPU_BANK_SIZE; in _is_enabled_region() local
153 _bank_select(bank); in _is_enabled_region()
166 uint32_t bank = r_index / ARC_FEATURE_MPU_BANK_SIZE; in _is_in_region() local
169 _bank_select(bank); in _is_in_region()
188 uint32_t bank = r_index / ARC_FEATURE_MPU_BANK_SIZE; in _is_user_accessible_region() local
[all …]
/Zephyr-latest/drivers/memc/
Dmemc_sam_smc.c37 SmcCs_number *bank; in memc_smc_init() local
53 bank = &cfg->regs->SMC_CS_NUMBER[cfg->banks[i].cs]; in memc_smc_init()
55 bank->SMC_SETUP = cfg->banks[i].setup_timing; in memc_smc_init()
56 bank->SMC_PULSE = cfg->banks[i].pulse_timing; in memc_smc_init()
57 bank->SMC_CYCLE = cfg->banks[i].cycle_timing; in memc_smc_init()
58 bank->SMC_MODE = cfg->banks[i].mode; in memc_smc_init()
/Zephyr-latest/soc/nxp/lpc/lpc54xxx/
DKconfig65 SRAM2 ram bank is disabled out of reset. By default, CMSIS SystemInit
66 will enable the clock to this RAM bank. Disable this Kconfig to leave
67 this ram bank untouched out of reset.
/Zephyr-latest/arch/arc/core/
Dfast_irq.S29 * The processor switches to a second register bank so registers from the
30 * current bank do not have to be preserved yet. The only issue is the LP_START/
48 * If CONFIG_RGF_NUM_BANKS>1, firq uses a 2nd register bank so GPRs do
89 * switch back to original register bank to get correct sp.
107 /* here, bank 0 sp must go back to the value before push and
180 * bank switch
188 * point, so when switching back to register bank 0, it will contain the
202 * sp<-reg bank'sp
215 /* chose register bank #0 */
297 /* LP registers are already restored, just switch back to bank 0 */
/Zephyr-latest/drivers/flash/
DKconfig.renesas_ra29 bool "Dual bank mode"
31 Enable dual bank mode
/Zephyr-latest/soc/snps/arc_iot/
Dsysconf.c171 void arc_iot_gpio8b_dbclk_div(uint8_t bank, uint8_t div) in arc_iot_gpio8b_dbclk_div() argument
173 if (bank == GPIO8B_BANK0) { in arc_iot_gpio8b_dbclk_div()
176 } else if (bank == GPIO8B_BANK1) { in arc_iot_gpio8b_dbclk_div()
179 } else if (bank == GPIO8B_BANK2) { in arc_iot_gpio8b_dbclk_div()
182 } else if (bank == GPIO8B_BANK3) { in arc_iot_gpio8b_dbclk_div()
188 void arc_iot_gpio4b_dbclk_div(uint8_t bank, uint8_t div) in arc_iot_gpio4b_dbclk_div() argument
190 if (bank == GPIO4B_BANK0) { in arc_iot_gpio4b_dbclk_div()
193 } else if (bank == GPIO4B_BANK1) { in arc_iot_gpio4b_dbclk_div()
196 } else if (bank == GPIO4B_BANK2) { in arc_iot_gpio4b_dbclk_div()
/Zephyr-latest/boards/st/nucleo_l053r8/support/
Dopenocd.cfg11 # Add the second flash bank.
13 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
/Zephyr-latest/boards/st/nucleo_l073rz/support/
Dopenocd.cfg11 # Add the second flash bank.
13 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME

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