Searched +full:add +full:- +full:apt +full:- +full:repository (Results 1 – 8 of 8) sorted by relevance
| /Zephyr-latest/doc/develop/getting_started/ |
| D | installation_linux.rst | 22 use their own configuration files, most notably ``apt`` and
32 .. group-tab:: Ubuntu
34 .. code-block:: console
36 sudo apt-get update
37 sudo apt-get upgrade
39 .. group-tab:: Fedora
41 .. code-block:: console
45 .. group-tab:: Clear Linux
47 .. code-block:: console
51 .. group-tab:: Arch Linux
[all …]
|
| D | index.rst | 8 - Set up a command-line Zephyr development environment on Ubuntu, macOS, or
11 - Get the source code
12 - Build, flash, and run a sample application
23 .. group-tab:: Ubuntu
28 .. code-block:: bash
30 sudo apt update
31 sudo apt upgrade
33 .. group-tab:: macOS
39 <https://support.apple.com/en-us/HT201541>`_.
41 .. group-tab:: Windows
[all …]
|
| /Zephyr-latest/.github/workflows/ |
| D | doc-build.yml | 2 # SPDX-License-Identifier: Apache-2.0
8 - cron: '0 */3 * * *'
11 - v*
17 # The latest CMake available directly with apt is 3.18, but we need >=3.20
22 # and each sphinx-build process may use more than 2GiB of RAM.
26 doc-file-check:
28 runs-on: ubuntu-22.04
30 github.repository_owner == 'zephyrproject-rtos'
32 file_check: ${{ steps.check-doc-files.outputs.any_modified }}
34 - name: checkout
[all …]
|
| /Zephyr-latest/boards/telink/tlsr9518adk80d/doc/ |
| D | index.rst | 17 The TLSR9518A SoC integrates a powerful 32-bit RISC-V MCU, DSP, AI Engine, 2.4 GHz ISM Radio, 256
28 - RF conducted antenna
29 - 1 MB External Flash memory with reset button
30 - Chip reset button
31 - Mini USB interface
32 - 4-wire JTAG
33 - 4 LEDs, Key matrix up to 4 keys
34 - 2 line-in function (Dual Analog microphone supported when switching jumper from microphone path)
35 - Dual Digital microphone
36 - Stereo line-out
[all …]
|
| /Zephyr-latest/boards/enjoydigital/litex_vexriscv/doc/ |
| D | index.rst | 1 .. _litex-vexriscv:
10 <https://github.com/litex-hub/zephyr-on-litex-vexriscv>`_
11 or `LiteX SoC Builder <https://github.com/enjoy-digital/litex>`_
14 vendor-specific and open-source tools, including the
19 `Digilent Arty A7-35T or A7-100T Development Boards
20 <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists>`_
21 or `SDI-MIPI Video Converter <https://github.com/antmicro/sdi-mipi-video-converter>`_.
28 `Migen <https://m-labs.hk/gateware/migen/>`_/`MiSoC SoC builder <https://github.com/m-labs/misoc>`_
29 and provides ready-made system components such as buses, streams, interconnects,
34 `LiteX's website <https://github.com/enjoy-digital/litex>`_.
[all …]
|
| /Zephyr-latest/doc/contribute/documentation/ |
| D | generation.rst | 11 .. _documentation-overview:
18 using Sphinx to create a formatted stand-alone website. Developers can
36 * Doxygen-generated material used to create all API-specific documents
39 * Script-generated material for kernel configuration options based on Kconfig
51 rtd [shape="rectangle" label="read-the-docs\ntheme"]
56 images -> sphinx
57 rst -> sphinx
58 conf -> sphinx
59 header -> doxygen
60 doxygen -> xml
[all …]
|
| /Zephyr-latest/boards/native/native_sim/doc/ |
| D | index.rst | 3 Native simulator - native_sim
63 .. zephyr-app-commands::
64 :zephyr-app: samples/hello_world
65 :host-os: unix
77 .. code-block:: console
84 You can run it with the ``--help`` command line switch to get a list of
87 .. code-block:: console
89 $ ./build/zephyr/zephyr.exe --help
95 Application tests using the :ref:`ztest framework<test-framework>` will exit after all
99 you may add a conditionally compiled (:kconfig:option:`CONFIG_ARCH_POSIX`) call to
[all …]
|
| /Zephyr-latest/boards/openisa/rv32m1_vega/doc/ |
| D | index.rst | 8 The VEGAboard contains the RV32M1 SoC, featuring two RISC-V CPUs,
9 on-die XIP flash, and a full complement of peripherals, including a
10 2.4 GHz multi-protocol radio. It also has built-in sensors and
11 Arduino-style expansion connectors.
13 The two RISC-V CPUs are named RI5CY and ZERO-RISCY, and are
15 `RI5CY`_ and `ZERO-RISCY`_. RI5CY is the "main" core; it has more
16 flash and RAM as well as a more powerful CPU design. ZERO-RISCY is a
17 "secondary" core. The main ZERO-RISCY use-case is as a wireless
30 RV32M1 multi-core SoC:
32 - 1 MiB flash and 192 KiB SRAM (RI5CY core)
[all …]
|
