Lines Matching +full:add +full:- +full:apt +full:- +full:repository
8 The VEGAboard contains the RV32M1 SoC, featuring two RISC-V CPUs,
9 on-die XIP flash, and a full complement of peripherals, including a
10 2.4 GHz multi-protocol radio. It also has built-in sensors and
11 Arduino-style expansion connectors.
13 The two RISC-V CPUs are named RI5CY and ZERO-RISCY, and are
15 `RI5CY`_ and `ZERO-RISCY`_. RI5CY is the "main" core; it has more
16 flash and RAM as well as a more powerful CPU design. ZERO-RISCY is a
17 "secondary" core. The main ZERO-RISCY use-case is as a wireless
30 RV32M1 multi-core SoC:
32 - 1 MiB flash and 192 KiB SRAM (RI5CY core)
33 - 256 KiB flash and 128 KiB SRAM (ZERO-RISCY core)
34 - Low power modes
35 - DMA support
36 - Watchdog, CRC, cryptographic acceleration, ADC, DAC, comparator,
38 card, USB full-speed, uSDHC, and 2.4 GHz multiprotocol radio
41 On-board sensors and peripherals:
43 - 32 Mbit SPI flash
44 - 6-axis accelerometer, magnetometer, and temperature sensor (FXOS8700)
45 - Ambient light sensor
46 - RGB LED
47 - microSD card slot
48 - Antenna interface
52 - Form-factor compatible with Arduino Uno Rev 3 expansion connector
53 layout (not all Arduino shields may be pin-compatible)
54 - UART via USB using separate OpenSDA chip
55 - RISC-V flash and debug using external JTAG dongle (not included) via
56 2x5 5 mil pitch connector (commonly called the "ARM 10-pin JTAG"
65 +-----------+------------+-------------------------------------+
68 | EVENT | on-chip | event unit interrupt controller |
69 +-----------+------------+-------------------------------------+
70 | INTMUX | on-chip | level 2 interrupt controller |
71 +-----------+------------+-------------------------------------+
72 | LPTMR | on-chip | lptmr-based system timer |
73 +-----------+------------+-------------------------------------+
74 | PINMUX | on-chip | pinmux |
75 +-----------+------------+-------------------------------------+
76 | GPIO | on-chip | gpio |
77 +-----------+------------+-------------------------------------+
78 | UART | on-chip | serial |
79 +-----------+------------+-------------------------------------+
80 | I2C(M) | on-chip | i2c |
81 +-----------+------------+-------------------------------------+
82 | SPI | on-chip | spi |
83 +-----------+------------+-------------------------------------+
84 | TPM | on-chip | pwm |
85 +-----------+------------+-------------------------------------+
86 | SENSOR | off-chip | fxos8700 polling; |
88 +-----------+------------+-------------------------------------+
90 Zephyr's ZERO-RISCY configuration, ``rv32m1_vega/openisa_rv32m1/zero_riscy``, currently
93 +-----------+------------+-------------------------------------+
96 | EVENT | on-chip | event unit interrupt controller |
97 +-----------+------------+-------------------------------------+
98 | INTMUX | on-chip | level 2 interrupt controller |
99 +-----------+------------+-------------------------------------+
100 | LPTMR | on-chip | lptmr-based system timer |
101 +-----------+------------+-------------------------------------+
102 | PINMUX | on-chip | pinmux |
103 +-----------+------------+-------------------------------------+
104 | GPIO | on-chip | gpio |
105 +-----------+------------+-------------------------------------+
106 | UART | on-chip | serial |
107 +-----------+------------+-------------------------------------+
108 | I2C(M) | on-chip | i2c |
109 +-----------+------------+-------------------------------------+
110 | TPM | on-chip | pwm |
111 +-----------+------------+-------------------------------------+
112 | SENSOR | off-chip | fxos8700 polling; |
114 +-----------+------------+-------------------------------------+
120 framework by Nordic Semi to enable the on-SoC radio and transceiver for
125 - beacon
126 - central
127 - central_hr
128 - eddystone
129 - hci_uart
130 - ibeacon
131 - peripheral_csc (Cycling Speed Cadence)
132 - peripheral_dis (Device Information Service)
133 - peripheral_esp (Environmental Sensing Service)
134 - peripheral_hr (Heart Rate)
135 - peripheral_ht (Health Thermometer)
136 - peripheral
137 - scan_adv
143 - no 512/256 Kbps PHY
144 - no TX power adjustment
150 RV32M1 SoC pins are brought out to Arduino-style expansion connectors.
156 the odd- and even-numbered pins are listed in separate tables. The
229 14 - GND
230 16 - AREF
237 Note that the headers at the bottom of the board have odd-numbered
255 Even/bottom pins: note that these are mostly power-related.
260 2 - SDA_GPIO0
261 4 - BRD_IO_PER
262 6 - RST_SDA
263 8 - BRD_IO_PER
264 10 - P5V_INPUT
265 12 - GND
266 14 - GND
267 16 - P5-9V VIN
272 Note that the headers at the bottom of the board have odd-numbered
280 1 - TAMPER2
281 3 - TAMPER1/RTC_CLKOUT
282 5 - TAMPER0/RTC_WAKEUP_b
285 11 - DAC0_OUT/ADC0_SE16/LPCMP0_IN3/LPCMP1_IN3
302 ---------------
304 For an up-to-date description of additional pins (such as buttons,
309 ZERO-RISCY.
317 The RI5CY and ZERO-RISCY cores are configured to use the slow internal
327 connected to the LPUART0 peripheral which the RI5CY and ZERO-RISCY cores use by
332 The OpenSDA chip cannot be used to flash or debug the RISC-V cores.
335 RISC-V cores using an external JTAG dongle.
340 .. _rv32m1-programming-hw:
346 - a `SEGGER J-Link`_ debug probe to debug the RISC-V cores
347 - a J-Link `9-Pin Cortex-M Adapter`_ board and ribbon cable
348 - the SEGGER `J-Link Software and Documentation Pack`_ software
361 .. _rv32m1-toolchain-openocd:
367 toolchain and an OpenOCD build. There are vendor-specific versions of
371 ------------------------------------------------------
376 - :file:`Toolchain_Linux.tar.gz`
377 - :file:`Toolchain_Mac.tar.gz`
378 - :file:`Toolchain_Windows.zip`
387 tar xvzf riscv32-unknown-elf-gcc.tar.gz
388 mv openocd ~/rv32m1-openocd
389 mv riscv32-unknown-elf-gcc ~
392 :file:`riscv32-unknown-elf-gcc.tar.gz` file doesn't expand into a
393 :file:`riscv32-unknown-elf-gcc` directory, so it has to be created)::
397 mkdir riscv32-unknown-elf-gcc
398 mv riscv32-unknown-elf-gcc.tar.gz riscv32-unknown-elf-gcc
399 cd riscv32-unknown-elf-gcc/
400 tar xvzf riscv32-unknown-elf-gcc.tar.gz
402 mv openocd ~/rv32m1-openocd
403 mv riscv32-unknown-elf-gcc ~
408 #. Extract the :file:`openocd.zip` and :file:`riscv32-unknown-elf-gcc.zip` files
410 #. Move the extracted :file:`openocd` folder to :file:`C:\\rv32m1-openocd`
411 #. Move the extracted :file:`riscv32-unknown-elf-gcc` folder to
412 :file:`C:\\riscv32-unknown-elf-gcc`
416 - You put the extracted toolchain at :file:`~/riscv32-unknown-elf-gcc`
417 on macOS or Linux, and :file:`C:\\riscv32-unknown-elf-gcc` on
419 - You put the extracted OpenOCD binary at :file:`~/rv32m1-openocd` on
420 macOS or Linux, and the OpenOCD folder into :file:`C:\\rv32m1-openocd`
425 - If you put the toolchain somewhere else, you will need to change
427 - If you put OpenOCD somewhere else, you will need to change the
429 - Don't use installation directories with spaces anywhere in the path;
433 ----------------------------------------------------
437 .. _rv32m1-vega-jtag:
442 This section describes how to connect to your board via the J-Link
444 <rv32m1-programming-hw>` for details on required hardware.
446 #. Connect the J-Link debugger through the adapter board to the
451 :alt: RV32M1-VEGA
453 VEGAboard connected properly to J-Link debugger.
459 #. Make sure your J-Link is connected to your computer via USB.
461 One-Time Board Setup For Booting RI5CY or ZERO-RISCY
464 Next, you'll need to make sure your board boots the RI5CY or ZERO-RISCY core.
476 to install the `60-openocd.rules`_ udev rules file (usually by
478 plugging the J-Link in again via USB).
482 These Zephyr-specific instructions differ slightly from the
488 ~/rv32m1-openocd -f boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg
492 .. code-block:: console
494 $ ~/rv32m1-openocd -f boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg
495 Open On-Chip Debugger 0.10.0+dev-00431-ge1ec3c7d (2018-10-31-07:29)
509 Open On-Chip Debugger
513 To boot the ZERO-RISCY core instead, replace ``ri5cy_boot`` above with
525 3. Unplug your J-Link and VEGAboard, and plug them back in.
531 …C:\rv32m1-openocd\bin\openocd.exe rv32m1-openocd -f boards\openisa\rv32m1_vega\support\openocd_rv3…
538 #. Unplug your J-Link and VEGAboard, and plug them back in.
540 To boot the ZERO-RISCY core instead, replace ``ri5cy_boot`` above with
549 cloned the Zephyr repository, and installed Python dependencies as
553 and OpenOCD as described above in :ref:`rv32m1-toolchain-openocd`.
559 export ZEPHYR_TOOLCHAIN_VARIANT=cross-compile
560 export CROSS_COMPILE=~/riscv32-unknown-elf-gcc/bin/riscv32-unknown-elf-
563 set ZEPHYR_TOOLCHAIN_VARIANT=cross-compile
564 set CROSS_COMPILE=C:\riscv32-unknown-elf-gcc\bin\riscv32-unknown-elf-
571 Now let's compile the :zephyr:code-sample:`hello_world` application. (You can try
572 others as well; see :zephyr:code-sample-category:`samples` for more.)
574 .. We can't use zephyr-app-commands to provide build instructions
577 Due to a toolchain `linker issue`_, you need to add an option setting
584 source zephyr-env.sh
586 .. zephyr-app-commands::
587 :zephyr-app: samples/hello_world
589 :cd-into:
591 :gen-args: -DCMAKE_REQUIRED_FLAGS=-Wl,-dT=/dev/null
597 zephyr-env.cmd
601 # Use CMake to generate a Ninja-based build system:
603 …cmake -GNinja -DBOARD=rv32m1_vega/openisa_rv32m1/ri5cy -DCMAKE_REQUIRED_FLAGS=-Wl,-dT=%cd%\empty.l…
613 Make sure you've done the :ref:`JTAG setup <rv32m1-vega-jtag>`, and
620 to install the `60-openocd.rules`_ udev rules file (usually by
622 plugging the J-Link in again via USB).
628 by using :ref:`west flash <west-build-flash-debug>` instead of ``ninja
636 # Don't use "~/rv32m1-openocd". It won't work.
637 west flash --openocd=$HOME/rv32m1-openocd
641 west flash --openocd=C:\rv32m1-openocd\bin\openocd.exe
645 - Make sure you don't have another ``openocd`` process running in the
647 - Unplug the boards and plug them back in.
648 - On Linux, make sure udev rules are installed, as described above.
658 Make sure you've done the :ref:`JTAG setup <rv32m1-vega-jtag>`, and
665 to install the `60-openocd.rules`_ udev rules file (usually by
667 plugging the J-Link in again via USB).
675 west debug --openocd=$HOME/rv32m1-openocd
678 west debug --openocd=C:\rv32m1-openocd\bin\openocd.exe
681 load the binary (:file:`zephyr.elf`), and re-sync with the OpenOCD
704 - Make sure you don't have another ``openocd`` process running in the
706 - Unplug the boards and plug them back in.
707 - On Linux, make sure udev rules are installed, as described above.
712 - OpenISA developer portal: http://open-isa.org
713 - `OpenISA GitHub releases`_: includes toolchain and OpenOCD
716 - Base toolchain: `pulp-riscv-gnu-toolchain`_; extra toolchain patches:
718 - OpenOCD repository: `rv32m1-openocd`_ (only needed if building from
720 - Vendor SDK: `rv32m1_sdk_riscv`_. Contains HALs, non-Zephyr sample
744 sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \
745 libmpfr-dev libgmp-dev gawk build-essential bison \
746 flex texinfo gperf libtool patchutils bc zlib1g-dev \
747 libusb-1.0-0-dev libudev1 libudev-dev g++
754 brew install gawk gnu-sed gmp mpfr libmpc isl zlib
756 The build toolchain is based on the `pulp-riscv-gnu-toolchain`_, with
757 some additional patches hosted in a separate repository,
759 instructions in the ``rv32m1_gnu_toolchain_patch`` repository's
762 …./configure --prefix=<toolchain-installation-dir> --with-arch=rv32imc --with-cmodel=medlow --enabl…
765 If you set ``<toolchain-installation-dir>`` to
766 :file:`~/riscv32-unknown-elf-gcc`, you can use the above instructions
776 if you want to set ``--prefix`` to a system directory such as
779 To build OpenOCD, clone the `rv32m1-openocd`_ repository, then run
780 these from the repository top level::
783 ./configure --prefix=<openocd-installation-dir>
787 If ``<openocd-installation-dir>`` is :file:`~/rv32m1-openocd`, you
788 should set your OpenOCD path to :file:`~/rv32m1-openocd/bin/openocd`
792 https://github.com/pulp-platform/riscv
793 .. _ZERO-RISCY:
794 https://github.com/pulp-platform/zero-riscy
796 http://iis-projects.ee.ethz.ch/index.php/PULP
798 .. _pulp-riscv-gnu-toolchain:
799 https://github.com/pulp-platform/pulp-riscv-gnu-toolchain
801 https://github.com/open-isa-rv32m1/rv32m1_gnu_toolchain_patch
802 .. _rv32m1-openocd:
803 https://github.com/open-isa-rv32m1/rv32m1-openocd
805 https://github.com/open-isa-rv32m1/rv32m1_gnu_toolchain_patch/blob/master/readme.md
807 https://github.com/open-isa-org/open-isa.org/releases
809 https://github.com/open-isa-rv32m1/rv32m1_sdk_riscv
811 https://github.com/pulp-platform/pulpino/issues/240
812 .. _60-openocd.rules:
813 https://github.com/open-isa-rv32m1/rv32m1-openocd/blob/master/contrib/60-openocd.rules
814 .. _SEGGER J-Link:
815 https://www.segger.com/products/debug-probes/j-link/
816 .. _9-Pin Cortex-M Adapter:
817 https://www.segger.com/products/debug-probes/j-link/accessories/adapters/9-pin-cortex-m-adapter/
818 .. _J-Link Software and Documentation Pack:
819 https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack
821 https://github.com/open-isa-rv32m1/rv32m1_sdk_riscv/blob/master/readme.md
827 For Linux users, the RISC-V toolchain in the :ref:`Zephyr SDK
829 SoC, and will not allow use of any available RISC-V ISA extensions.
832 upstream repository or the OpenOCD build in the Zephyr SDK.