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/Zephyr-Core-2.7.6/dts/bindings/rtc/
Dxlnx,xps-timer-1.00.a.yaml3 compatible: "xlnx,xps-timer-1.00.a"
8 # https://github.com/Xilinx/meta-xilinx
11 clock-frequency:
14 xlnx,count-width:
18 - 8
19 - 16
20 - 32
24 xlnx,gen0-assert:
28 - 0
29 - 1
[all …]
/Zephyr-Core-2.7.6/tests/drivers/gpio/gpio_basic_api/src/
Dtest_gpio_port.c4 * SPDX-License-Identifier: Apache-2.0
10 #define ALL_BITS ((gpio_port_value_t)-1)
14 /* Short-hand for a checked read of PIN_IN raw state */
25 /* Short-hand for a checked read of PIN_IN logical state */
36 /* Short-hand for a checked write of PIN_OUT raw state */
50 /* Short-hand for a checked write of PIN_OUT logic state */
93 TC_PRINT("FATAL output pin not wired to input pin? (out low => in high)\n"); in setup()
104 if (rc == -ENOTSUP) { in setup()
111 /* Test output high */ in setup()
114 "pin config output high failed"); in setup()
[all …]
/Zephyr-Core-2.7.6/dts/bindings/ieee802154/
Ddecawave,dw1000.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: spi-device.yaml
11 int-gpios:
12 type: phandle-array
16 The interrupt pin IRQ of DW1000 is active high output.
18 as active high.
20 reset-gpios:
21 type: phandle-array
25 The RESET pin of DW1000 is active low.
27 as active low.
[all …]
/Zephyr-Core-2.7.6/dts/bindings/sensor/
Dlm77.yaml2 # SPDX-License-Identifier: Apache-2.0
9 include: i2c-device.yaml
12 int-gpios:
13 type: phandle-array
16 Identifies the INT signal, which is active-low open drain by default
19 int-inverted:
22 When present, the polarity on the INT signal is inverted (active-high).
24 tcrita-inverted:
28 (active-high).
30 enable-fault-queue:
Dnxp,fxos8700.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: FXOS8700 6-axis accelerometer/magnetometer sensor
8 include: i2c-device.yaml
11 reset-gpios:
12 type: phandle-array
16 This pin defaults to active high when consumed by the sensor.
20 int1-gpios:
21 type: phandle-array
25 This pin defaults to active low when produced by the sensor.
29 int2-gpios:
[all …]
Dadi,adxl372-i2c.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ADXL372 3-axis high-g I2C/SPI accelerometer
8 include: i2c-device.yaml
11 int1-gpios:
12 type: phandle-array
15 The INT1 signal defaults to active high as produced by the
Dadi,adxl372-spi.yaml3 # SPDX-License-Identifier: Apache-2.0
5 description: ADXL372 3-axis high-g accelerometer, accessed through SPI bus
9 include: spi-device.yaml
12 int1-gpios:
13 type: phandle-array
16 The INT1 signal defaults to active high as produced by the
Dti,fdc2x1x.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: i2c-device.yaml
11 sd-gpios:
12 type: phandle-array
15 The SD pin defaults to active high when consumed by the sensor.
19 intb-gpios:
20 type: phandle-array
23 The INTB pin defaults to active low when produced by the sensor.
30 Set to identify the sensor as FDC2114 or FDC2214 (4-channel version)
35 Set the Auto-Scan Mode.
[all …]
Dst,lsm6dsl-i2c.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: STMicroelectronics LSM6DSL 6-axis accelerometer and gyrometer
8 include: i2c-device.yaml
11 irq-gpios:
12 # This signal is active high when produced by the sensor
13 type: phandle-array
Dst,lsm6dsl-spi.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STMicroelectronics LSM6DSL 6-axis accelerometer and gyrometer accessed
10 include: spi-device.yaml
13 irq-gpios:
14 # This signal is active high when produced by the sensor
15 type: phandle-array
Dadi,adxl362.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ADXL362 3-axis SPI accelerometer
8 include: spi-device.yaml
11 int1-gpios:
12 type: phandle-array
15 The INT1 signal defaults to active high as produced by the
Dst,lis2ds12-i2c.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: STMicroelectronics LIS2DS12 3-axis accelerometer
8 include: i2c-device.yaml
11 irq-gpios:
12 type: phandle-array
16 This pin defaults to active high when produced by the sensor.
Dst,lis3mdl-magn.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,lis3mdl-magn"
8 include: i2c-device.yaml
11 irq-gpios:
13 type: phandle-array
16 This pin defaults to active high when produced by the sensor.
Dst,iis2mdc-i2c.yaml2 # SPDX-License-Identifier: Apache-2.0
9 include: i2c-device.yaml
12 drdy-gpios:
13 type: phandle-array
17 This pin defaults to active high when produced by the sensor.
/Zephyr-Core-2.7.6/dts/bindings/display/
Dsolomon,ssd16xx.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: spi-device.yaml
21 pp-height-bits:
26 pp-width-bits:
32 type: uint8-array
37 type: uint8-array
46 border-waveform:
52 type: uint8-array
56 orientation-flipped:
61 reset-gpios:
[all …]
Dftdi,ft800.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: spi-device.yaml
11 irq-gpios:
12 type: phandle-array
36 Controls the transition of RGB signals with PCLK active clock
38 following the active edge of PCLK. When set to 1, R[7:2]
71 Number of lines for the high state of signal VSYNC at
101 description: Number of PCLK cycles of HSYNC high state during start of
/Zephyr-Core-2.7.6/dts/bindings/lora/
Dsemtech,sx127x-base.yaml3 # SPDX-License-Identifier: Apache-2.0
5 include: spi-device.yaml
8 reset-gpios:
9 type: phandle-array
14 This signal is open-drain, active-high (SX1272/3) or
15 active-low (SX1276/7/8/9) as interpreted by the modem.
17 dio-gpios:
18 type: phandle-array
23 These signals are normally active-high.
25 power-amplifier-output:
[all …]
/Zephyr-Core-2.7.6/include/dt-bindings/pinctrl/
Dnpcx-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
20 * Power Switch Logic (PSL) input wake-up mode is sensitive to edge signals.
28 * Power Switch Logic (PSL) input wake-up mode is sensitive to logical levels.
36 * The active polarity of Power Switch Logic (PSL) input is high level or
37 * low-to-high transition.
45 * The active polarity of Power Switch Logic (PSL) input is low level or
46 * high-to-low transition.
57 * 'nuvoton,npcx-pslctrl-conf' compatible.
65 * 'nuvoton,npcx-pslctrl-conf' compatible.
70 * Configures Power Switch Logic (PSL) input in detecting level high state (has
[all …]
/Zephyr-Core-2.7.6/tests/drivers/gpio/gpio_api_1pin/src/
Dtest_pin_interrupt.c4 * SPDX-License-Identifier: Apache-2.0
62 if (ret == -ENOTSUP) { in test_gpio_pin_interrupt_edge()
85 if (ret == -ENOTSUP) { in test_gpio_pin_interrupt_edge()
99 "number of times on rising/to active edge", i); in test_gpio_pin_interrupt_edge()
136 if (ret == -ENOTSUP) { in test_gpio_pin_interrupt_level()
164 if (ret == -ENOTSUP) { in test_gpio_pin_interrupt_level()
188 /* Re-enable pin level interrupt */ in test_gpio_pin_interrupt_level()
191 "Failed to re-enable pin level interrupt"); in test_gpio_pin_interrupt_level()
226 TC_PRINT("Step 1: Configure pin as active high\n"); in test_gpio_int_edge_to_active()
228 TC_PRINT("Step 2: Configure pin as active low\n"); in test_gpio_int_edge_to_active()
[all …]
/Zephyr-Core-2.7.6/dts/bindings/misc/
Dzephyr,modbus-serial.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "zephyr,modbus-serial"
8 include: uart-device.yaml
11 de-gpios:
12 type: phandle-array
16 Driver enable pin (DE) of the RS-485 transceiver.
18 as active high.
20 re-gpios:
21 type: phandle-array
25 Receiver enable pin (nRE) of the RS-485 transceiver.
[all …]
/Zephyr-Core-2.7.6/include/drivers/
Dgpio.h2 * Copyright (c) 2019-2020 Nordic Semiconductor ASA
5 * Copyright (c) 2015-2016 Intel Corporation.
7 * SPDX-License-Identifier: Apache-2.0
24 #include <dt-bindings/gpio/gpio.h>
56 /* Initializes output to a high state. */
66 /** Configures GPIO pin as output and initializes it to a high state. */
84 * flag. If a pin was configured as Active Low, physical level low will be
85 * considered as logical level 1 (an active state), physical level high will
122 /* Trigger detection on input state is (or transitions to) physical high or
166 /** Configures GPIO interrupt to be triggered on pin physical level high and
[all …]
/Zephyr-Core-2.7.6/include/dt-bindings/pwm/
Dpwm.h4 * SPDX-License-Identifier: Apache-2.0
16 /** PWM pin normal polarity (active-high pulse). */
19 /** PWM pin inverted polarity (active-low pulse). */
/Zephyr-Core-2.7.6/dts/bindings/gpio/
Dsemtech,sx1509b-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [i2c-device.yaml, gpio-controller.yaml]
14 "#gpio-cells":
21 nint-gpios:
22 type: phandle-array
25 Connection for the NINT signal. This signal is active-low when
28 init-out-low:
36 init-out-high:
42 driven high.
44 gpio-cells:
[all …]
/Zephyr-Core-2.7.6/samples/boards/up_squared/gpio_counter/
DREADME.rst11 The sample enables a pin as GPIO input (active high) that triggers the increment
14 represented on GPIO output (active high) as a 4-bit value
15 (bin 0, 1, 2, 3 -> HAT Pin 35, 37, 38, 40).
17 +------------+-----------------------------+
21 +------------+-----+-----+-----+-----+-----+
23 +------------+-----+-----+-----+-----+-----+
25 +------------+-----+-----+-----+-----+-----+
27 +------------+-----+-----+-----+-----+-----+
28 | Active | H | H | H | H | H |
29 +------------+-----+-----+-----+-----+-----+
[all …]
/Zephyr-Core-2.7.6/dts/bindings/mmc/
Dnxp,imx-usdhc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,imx-usdhc"
14 pwr-gpios:
15 type: phandle-array
19 This pin defaults to active high when consumed by the SD card. The
23 cd-gpios:
24 type: phandle-array
28 This pin defaults to active low when produced by the SD card. The
32 no-1-8-v:

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