Searched +full:xl +full:- +full:density (Results 1 – 2 of 2) sorted by relevance
3 # Copyright (c) 2016 Open-RnD Sp. z o.o.5 # SPDX-License-Identifier: Apache-2.056 * Low density Value line devices57 * Medium density Value line devices58 * High density Value line devices59 * XL-density devices Value line devices66 connectivity and real-time performances are required such as
2 # SPDX-License-Identifier: Apache-2.05 Main PLL node binding for low-, medium-, high- and XL-density STM32F1 devices.12 f(PLLCLK) = f(input clk) x PLLMUL --> SYSCLK (System Clock)17 compatible: "st,stm32f1-pll-clock"19 include: [clock-controller.yaml, base.yaml]22 "#clock-cells":33 Valid range: 2 - 16
