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| /Zephyr-Core-3.4.0/doc/services/pm/images/ |
| D | devr-async-ops.svg | 1 …x2="68" y1="36.2969" y2="468.6266"/><line style="stroke:#000000;stroke-width:1.0;stroke-dasharray:…
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| D | devr-sync-ops.svg | 1 …x2="68" y1="36.2969" y2="455.961"/><line style="stroke:#000000;stroke-width:1.0;stroke-dasharray:5…
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| /Zephyr-Core-3.4.0/arch/arm64/core/ |
| D | switch.S | 57 lsr x2, x4, #TPIDRROEL0_EXC_SHIFT
63 orr x4, x4, x2, lsl #TPIDRROEL0_EXC_SHIFT
84 ldr x2, [x0, #_thread_offset_to_tls]
90 msr tpidr_el0, x2
114 ldr x2, [x0, #_thread_offset_to_stack_limit]
115 str x2, [x4, #_cpu_offset_to_current_stack_limit]
183 get_cpu x2
184 ldr w3, [x2, #___cpu_t_nested_OFFSET]
186 str w4, [x2, #___cpu_t_nested_OFFSET]
190 ldr x3, [x2, #___cpu_t_irq_stack_OFFSET]
[all …]
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| D | isr_wrapper.S | 44 mov x2, sp
46 str x2, [sp, #-16]!
132 ldr x2, [x1, #_thread_offset_to_stack_limit]
133 str x2, [x0, #_cpu_offset_to_current_stack_limit]
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| D | reset.S | 127 ldaxr x2, [x0, #BOOT_PARAM_MPID_OFFSET]
128 cmp x2, #-1
137 ldr x2, [x0, #BOOT_PARAM_MPID_OFFSET]
138 cmp x1, x2
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| /Zephyr-Core-3.4.0/dts/bindings/dma/ |
| D | st,stm32u5-dma.yaml | 28 0x2: PERIPH to MEM
39 0x2: Word (32 bits)
44 0x2: Word (32 bits)
50 0x2: high
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| D | gd,gd32-dma.yaml | 13 - 0x2: PERIPH to MEMORY
27 - 0x2: 32 bits
33 - 0x2: 32 bits
43 - 0x2: high
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| D | gd,gd32-dma-v1.yaml | 15 - 0x2: PERIPH to MEMORY
29 - 0x2: 32 bits
35 - 0x2: 32 bits
45 - 0x2: high
52 - 0x2: 3 word
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| D | st,stm32-dma-v1.yaml | 22 0x2: PERIPH to MEM
33 0x2: Word (32 bits)
38 0x2: Word (32 bits)
46 0x2: high
52 0x2: 3/4 full FIFO
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| D | st,stm32-dmamux.yaml | 18 0x2: PERIPH to MEM
29 0x2: Word (32 bits)
34 0x2: Word (32 bits)
42 0x2: high
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| D | st,stm32-bdma.yaml | 20 0x2: PERIPH to MEM
31 0x2: Word (32 bits)
36 0x2: Word (32 bits)
44 0x2: high
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| D | st,stm32-dma-v2bis.yaml | 23 0x2: STM32_DMA_PERIPH_TO_MEMORY: PERIPH to MEM
34 0x2: STM32_DMA_PERIPH_32BITS: Word (32 bits)
39 0x2: STM32_DMA_MEM_32BITS: Word (32 bits)
45 0x2: STM32_DMA_PRIORITY_HIGH: high
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| D | st,stm32-dma-v2.yaml | 29 0x2: STM32_DMA_PERIPH_TO_MEMORY: PERIPH to MEM
40 0x2: STM32_DMA_PERIPH_32BITS: Word (32 bits)
45 0x2: STM32_DMA_MEM_32BITS: Word (32 bits)
51 0x2: STM32_DMA_PRIORITY_HIGH: high
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| /Zephyr-Core-3.4.0/dts/arm/nuvoton/npcx/ |
| D | npcx-alts-map.dtsi | 29 alts = <&scfg 0x01 0x2 0>;
55 alts = <&scfg 0x02 0x2 0>;
78 alts = <&scfg 0x03 0x2 0>;
98 alts = <&scfg 0x04 0x2 0>;
132 alts = <&scfg 0x06 0x2 0>;
158 alts = <&scfg 0x07 0x2 1>;
184 alts = <&scfg 0x08 0x2 1>;
210 alts = <&scfg 0x09 0x2 1>;
236 alts = <&scfg 0x0A 0x2 0>;
253 alts = <&scfg 0x0B 0x2 0>;
[all …]
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| /Zephyr-Core-3.4.0/include/zephyr/dt-bindings/pinctrl/ |
| D | esp-pinctrl-common.h | 45 #define ESP32_PULL_UP 0x2
50 #define ESP32_OPEN_DRAIN 0x2
57 #define ESP32_PIN_OUT_LOW 0x2
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| D | stm32-pinctrl.h | 20 #define STM32_AF2 0x2
84 #define STM32_MODER_ALT_MODE (0x2 << STM32_MODER_SHIFT)
98 #define STM32_OSPEEDR_HIGH_SPEED (0x2 << STM32_OSPEEDR_SHIFT)
106 #define STM32_PUPDR_PULL_DOWN (0x2 << STM32_PUPDR_SHIFT)
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| D | stm32f1-pinctrl.h | 56 #define ANALOG 0x2 /* Analog */
84 #define STM32_CNF_IN_PUPD (0x2 << STM32_CNF_IN_SHIFT)
91 #define STM32_MODE_OUTPUT_MAX_50 (0x2 << STM32_MODE_OSPEED_SHIFT)
108 #define STM32_PUPD_PULL_DOWN (0x2 << STM32_PUPD_SHIFT)
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| D | mchp-xec-pinctrl.h | 15 #define MCHP_AF2 0x2
36 #define MCHP_XEC_SLEW_RATE_FAST0 0x2
40 #define MCHP_XEC_DRV_STR0_2X 0x2 /* 4 or 8(PIO-24) mA */
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| /Zephyr-Core-3.4.0/drivers/sensor/bme280/ |
| D | Kconfig | 39 bool "x2"
57 bool "x2"
75 bool "x2"
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| /Zephyr-Core-3.4.0/drivers/sensor/bme680/ |
| D | Kconfig | 28 bool "x2"
46 bool "x2"
64 bool "x2"
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| /Zephyr-Core-3.4.0/drivers/sensor/dps310/ |
| D | Kconfig | 27 bool "x2"
51 bool "x2"
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| /Zephyr-Core-3.4.0/arch/arm/core/aarch32/mmu/ |
| D | arm_mmu_priv.h | 36 #define ARM_MMU_PTE_ID_SECTION 0x2
38 #define ARM_MMU_PTE_ID_SMALL_PAGE 0x2
40 #define ARM_MMU_PERMS_AP2_DISABLE_WR 0x2
45 #define ARM_MMU_TEX_CACHE_ATTRS_WT_nWA 0x2
63 #define ARM_MMU_TTBR_RGN_OUTER_WT_CACHEABLE 0x2
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| /Zephyr-Core-3.4.0/scripts/dts/python-devicetree/tests/ |
| D | test_edtlib.py | 112 …edtlib.Range(node=node, child_bus_cells=0x1, child_bus_addr=0x1, parent_bus_cells=0x2, parent_bus_…
113 …ild_bus_cells=0x1, child_bus_addr=0x2, parent_bus_cells=0x2, parent_bus_addr=0xc0000000d, length_c…
114 …edtlib.Range(node=node, child_bus_cells=0x1, child_bus_addr=0x4, parent_bus_cells=0x2, parent_bus_…
119 …ode=node, child_bus_cells=0x2, child_bus_addr=0x0, parent_bus_cells=0x3, parent_bus_addr=0x3000000…
124 …ls=0x1, child_bus_addr=0x0, parent_bus_cells=0x2, parent_bus_addr=0x200000000, length_cells=0x1, l…
145 …ld_bus_addr=0xa, parent_bus_cells=0x0, parent_bus_addr=None, length_cells=0x2, length=0xb0000000c),
146 …d_bus_addr=0x1a, parent_bus_cells=0x0, parent_bus_addr=None, length_cells=0x2, length=0x1b0000001c…
147 …d_bus_addr=0x2a, parent_bus_cells=0x0, parent_bus_addr=None, length_cells=0x2, length=0x2b0000002c)
152 …edtlib.Range(node=node, child_bus_cells=0x2, child_bus_addr=0xa0000000b, parent_bus_cells=0x1, par…
153 …edtlib.Range(node=node, child_bus_cells=0x2, child_bus_addr=0x1a0000001b, parent_bus_cells=0x1, pa…
[all …]
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| /Zephyr-Core-3.4.0/drivers/ethernet/ |
| D | eth_smsc91x_priv.h | 23 #define EPHSR 0x2
52 #define RPCR_LED_LINK_10 0x2 /* 10baseT link detected */
63 /* Bank 1, Offset 0x2: Base Address Register */
64 #define BAR 0x2
89 /* Bank2, Offset 0x2: Packet Number Register */
90 #define PNR 0x2
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| /Zephyr-Core-3.4.0/dts/bindings/timer/ |
| D | st,stm32-lptim.yaml | 46 Clock x2 factor at the input of the LPTIM,
48 For example, stm32U5x have a x2-factor for LPTIM1,3,4.
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