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/Zephyr-latest/boards/shields/x_nucleo_eeprma2/
Dx_nucleo_eeprma2.overlay30 /* if solder-bridge closed: arduino A1 pin on CN8 can wp */
31 /* wp-gpios = <&arduino_header 1 GPIO_ACTIVE_LOW>; */
43 /* if solder-bridge closed: arduino A1 pin on CN8 can wp */
44 /* wp-gpios = <&arduino_header 1 GPIO_ACTIVE_LOW>; */
56 /* if solder-bridge closed: arduino A1 pin on CN8 can wp */
57 /* wp-gpios = <&arduino_header 1 GPIO_ACTIVE_LOW>; */
93 /* if solder-bridge closed: arduino A0 pin on CN8 can wp */
94 /* wp-gpios = <&arduino_header 0 GPIO_ACTIVE_LOW>; */
107 /* if solder-bridge closed: arduino A0 pin on CN8 can wp */
108 /* wp-gpios = <&arduino_header 0 GPIO_ACTIVE_LOW>; */
[all …]
/Zephyr-latest/soc/espressif/common/
DKconfig.spiram209 bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)"
216 …When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
218 mode, so a WP pin setting is necessary.
220 If this config item is set to N (default), the correct WP pin will be automatically used for any
222 to Y and specify the GPIO number connected to the WP pin.
224 …When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP p…
228 int "Custom SPI PSRAM WP(SD3) Pin"
233 The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored
236 value to the GPIO number of the SPIRAM WP pin.
/Zephyr-latest/samples/drivers/mspi/mspi_flash/src/
Dmain.c65 const uint8_t *wp = expected; in single_sector_test() local
73 *wp, *rp, (*rp == *wp) ? "match" : "MISMATCH"); in single_sector_test()
75 ++wp; in single_sector_test()
148 const uint8_t *wp = expected; in multi_sector_test() local
156 *wp, *rp, (*rp == *wp) ? "match" : "MISMATCH"); in multi_sector_test()
158 ++wp; in multi_sector_test()
/Zephyr-latest/samples/drivers/spi_flash/src/
Dmain.c107 const uint8_t *wp = expected; in single_sector_test() local
115 *wp, *rp, (*rp == *wp) ? "match" : "MISMATCH"); in single_sector_test()
117 ++wp; in single_sector_test()
189 const uint8_t *wp = expected; in multi_sector_test() local
197 *wp, *rp, (*rp == *wp) ? "match" : "MISMATCH"); in multi_sector_test()
199 ++wp; in multi_sector_test()
/Zephyr-latest/tests/kernel/workq/work/src/
Dmain.c688 struct k_work *wp = &ctx->work; in ZTEST() local
694 k_work_init(wp, rel_handler); in ZTEST()
697 rc = k_work_submit_to_queue(&coophi_queue, wp); in ZTEST()
712 zassert_equal(k_work_cancel(wp), K_WORK_RUNNING | K_WORK_CANCELING, in ZTEST()
726 zassert_true(k_work_cancel_sync(wp, &work_sync)); in ZTEST()
741 rc = k_work_busy_get(wp); in ZTEST()
751 struct k_work *wp = &ctx->work; in ZTEST() local
757 k_work_init(wp, rel_handler); in ZTEST()
760 rc = k_work_submit_to_queue(&coophi_queue, wp); in ZTEST()
775 zassert_true(k_work_cancel_sync(wp, &work_sync)); in ZTEST()
[all …]
/Zephyr-latest/tests/drivers/build_all/eeprom/
Dapp.overlay44 wp-gpios = <&test_gpio 0 0>;
54 wp-gpios = <&test_gpio 0 0>;
92 wp-gpios = <&test_gpio 0 0>;
/Zephyr-latest/drivers/flash/
Dspi_flash_at45.c70 const struct gpio_dt_spec *wp; member
339 if (cfg->wp) { in spi_flash_at45_write()
340 gpio_pin_set_dt(cfg->wp, 0); in spi_flash_at45_write()
365 if (cfg->wp) { in spi_flash_at45_write()
366 gpio_pin_set_dt(cfg->wp, 1); in spi_flash_at45_write()
455 if (cfg->wp) { in spi_flash_at45_erase()
456 gpio_pin_set_dt(cfg->wp, 0); in spi_flash_at45_erase()
508 if (cfg->wp) { in spi_flash_at45_erase()
509 gpio_pin_set_dt(cfg->wp, 1); in spi_flash_at45_erase()
580 if (dev_config->wp) { in spi_flash_at45_init()
[all …]
/Zephyr-latest/tests/drivers/flash/common/boards/
Dnrf52840dk_spi_nor_wp_hold.overlay6 * Build test for jedec,spi-nor compatible (drivers/flash/spi_nor.c) wp-gpios and hold-gpios
45 wp-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
/Zephyr-latest/samples/bluetooth/channel_sounding/
DREADME.rst130 … Core Specification v. 6.0: Vol. 1, Part A, 9.2 <https://www.bluetooth.com/wp-content/uploads/File…
131 … Core Specification v. 6.0: Vol. 1, Part A, 9.3 <https://www.bluetooth.com/wp-content/uploads/File…
132 …Core Specification v. 6.0: Vol. 6, Part D, 6.34 <https://www.bluetooth.com/wp-content/uploads/File…
133 …Core Specification v. 6.0: Vol. 6, Part D, 6.35 <https://www.bluetooth.com/wp-content/uploads/File…
/Zephyr-latest/drivers/crypto/
Dcrypto_intel_sha_registers.h57 uint32_t wp : 24; member
73 uint32_t wp : 24; member
/Zephyr-latest/dts/bindings/mtd/
Dandestech,qspi-nor.yaml16 wp-gpios:
Djedec,spi-nor.yaml15 wp-gpios:
Datmel,at45.yaml92 wp-gpios:
95 The WP pin of AT45 is active low.
Datmel,at2x-base.yaml23 wp-gpios:
Dfujitsu,mb85rcxx.yaml26 wp-gpios:
/Zephyr-latest/tests/drivers/mspi/flash/src/
Dmain.c161 const uint8_t *wp = expected; in test_multi_sector_rw() local
168 if (*rp != *wp) { in test_multi_sector_rw()
170 (uint32_t)(offs + (rp - actual)), *wp, *rp); in test_multi_sector_rw()
178 ++wp; in test_multi_sector_rw()
/Zephyr-latest/drivers/sdhc/
Dsdhc_renesas_ra.h45 ret = -EACCES; /* SD card write-protected (requires WP sinal) */ in err_fsp2zep()
/Zephyr-latest/dts/bindings/spi/
Dmicrochip,xec-qmspi.yaml58 description: Delay in system clocks from CS# de-assertion to driving HOLD# and WP#
Dmicrochip,xec-qmspi-ldma.yaml72 and WP#. If not present use hardware default value. Refer to chip
/Zephyr-latest/samples/drivers/jesd216/boards/
Dnrf52840dk_nrf52840_spi.overlay33 wp-gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
/Zephyr-latest/dts/bindings/led_strip/
Dws2812.yaml13 https://wp.josh.com/2014/05/13/ws2812-neopixels-are-not-so-finicky-once-you-get-to-know-them/
/Zephyr-latest/include/zephyr/drivers/flash/
Dstm32_flash_api_extensions.h39 * After calling, it's not possible to change option bytes (WP, RDP,
/Zephyr-latest/tests/net/lib/lwm2m/interop/
DREADME.md66 java -jar ./leshan-server-demo.jar -wp 8080 -vv
67 java -jar ./leshan-bsserver-demo.jar -lp=5783 -slp=5784 -wp 8081
86 …--startas /bin/bash -- -c "exec java -jar ./leshan-server-demo.jar -wp 8080 -vv --models-folder ob…
89 …--startas /bin/bash -- -c "exec java -jar ./leshan-bsserver-demo.jar -lp=5783 -slp=5784 -wp 8081 -…
/Zephyr-latest/drivers/eeprom/
Deeprom_mb85rcxx.c86 LOG_ERR("wp gpio device not ready"); in mb85rcxx_init()
93 LOG_ERR("failed to configure WP GPIO pin (err %d)", err); in mb85rcxx_init()
/Zephyr-latest/soc/nuvoton/npcx/common/
Dsoc_pins.h51 * @brief Force the internal SPI flash write-protect pin (WP) to low level to

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