Searched full:ultrascale (Results 1 – 9 of 9) sorted by relevance
19 * which the UltraScale doesn't have. Contradicting information is provided in20 * the UltraScale TRM (UG1085), which mentions in chapter 34, section "Configure23 * on the UltraScale compared to the Zynq-7000.25 * to both the UltraScale and the Zynq-7000.
10 ZynqMP (UltraScale) SoCs. It interfaces both I/O pins of the SoC,24 ZynqMP (UltraScale) (comp. Ultrascale TRM, chap. 27, p. 769):
8 See Zynq UltraScale+ Devices Register Reference (UG1087) for details regarding
5 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
56 platforms such as ZynqMP Ultrascale+.
6 This board configuration will use QEMU to emulate the Xilinx Zynq UltraScale+103 3. Zynq UltraScale+ Device Technical Reference Manual (UG1085)
12 * Refer to the "Zynq UltraScale+ Device Technical Reference Manual" document
129 * UltraScale TX clock configuration: comp.130 * https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html578 * cpu_1x clock (Zynq-7000) or the LPD LSBUS clock (UltraScale).680 * UltraScale SoCs, which both contain the GEM.
152 3. Zynq UltraScale+ Device Technical Reference Manual (UG1085)
