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/Zephyr-latest/samples/boards/st/mco/boards/
Dnucleo_u5a5zj_q.overlay13 clocks = <&rcc STM32_SRC_LSE MCO1_SEL(MCO1_SEL_LSE)>;
Dstm32f746g_disco.overlay17 clocks = <&rcc STM32_SRC_LSE MCO1_SEL(MCO1_SEL_LSE)>;
Dnucleo_f446ze.overlay15 /* clocks = <&rcc STM32_SRC_LSE MCO1_SEL(1)>; */
Dnucleo_f411re.overlay15 /* clocks = <&rcc STM32_SRC_LSE MCO1_SEL(1)>; */
/Zephyr-latest/samples/boards/st/power_mgmt/serial_wakeup/boards/
Dnucleo_wl55jc.overlay11 <&rcc STM32_SRC_LSE LPUART1_SEL(3)>;
Dstm32l562e_dk.overlay24 <&rcc STM32_SRC_LSE LPUART1_SEL(3)>;
/Zephyr-latest/dts/bindings/clock/
Dst,stm32-clock-mco.yaml17 clocks = <&rcc STM32_SRC_LSE MCO1_SEL(7)>;
Dst,stm32f1-clock-mco.yaml19 clocks = <&rcc STM32_SRC_LSE MCO1_SEL(7)>;
/Zephyr-latest/boards/st/nucleo_wba52cg/
Dnucleo_wba52cg.dts93 <&rcc STM32_SRC_LSE RTC_SEL(1)>;
135 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
/Zephyr-latest/boards/st/stm32l562e_dk/
Dstm32l562e_dk_stm32l562xx_ns.dts33 <&rcc STM32_SRC_LSE RTC_SEL(1)>;
/Zephyr-latest/boards/weact/stm32g431_core/
Dweact_stm32g431_core.dts119 <&rcc STM32_SRC_LSE RTC_SEL(1)>;
125 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
/Zephyr-latest/boards/st/nucleo_wba55cg/
Dnucleo_wba55cg.dts112 <&rcc STM32_SRC_LSE RTC_SEL(1)>;
161 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dg0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay75 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
Dl4_i2c1_hsi_lptim1_lse.overlay83 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
Dwb_i2c1_hsi_lptim1_lse.overlay81 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
Dwl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay94 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32_common_clocks.h12 #define STM32_SRC_LSE 0x002 macro
/Zephyr-latest/boards/st/b_u585i_iot02a/
Db_u585i_iot02a-common.dtsi79 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
251 <&rcc STM32_SRC_LSE RTC_SEL(1)>;
/Zephyr-latest/boards/makerbase/mks_canable_v20/
Dmks_canable_v20.dts69 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
/Zephyr-latest/boards/st/nucleo_f070rb/
Dnucleo_f070rb.dts131 <&rcc STM32_SRC_LSE RTC_SEL(1)>;
/Zephyr-latest/boards/st/nucleo_c031c6/
Dnucleo_c031c6.dts91 <&rcc STM32_SRC_LSE RTC_SEL(1)>;
/Zephyr-latest/boards/st/nucleo_c071rb/
Dnucleo_c071rb.dts98 <&rcc STM32_SRC_LSE RTC_SEL(1)>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/
Dtest_stm32_clock_configuration_lptim.c51 if (pclken[1].bus == STM32_SRC_LSE) { in ZTEST()
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_common.c154 #if defined(STM32_SRC_LSE) in enabled_clock()
155 case STM32_SRC_LSE: in enabled_clock()
160 #endif /* STM32_SRC_LSE */ in enabled_clock()
454 #if defined(STM32_SRC_LSE) in stm32_clock_control_get_subsys_rate()
455 case STM32_SRC_LSE: in stm32_clock_control_get_subsys_rate()
/Zephyr-latest/boards/st/nucleo_h533re/
Dnucleo_h533re.dts162 <&rcc STM32_SRC_LSE RTC_SEL(1)>;

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