Searched full:sr1 (Results 1 – 11 of 11) sorted by relevance
| /Zephyr-Core-3.7.0/dts/bindings/spi/ |
| D | infineon,xmc4xxx-spi.yaml | 57 simple mapping: in USIC0 interrupt 84->SR0, interrupt 85->SR1, ... etc.
58 In USIC1, interrupt 90->SR0, 91->SR1, etc.
63 The interrupt would map to SR1. From Table "DMA Request Source Selection", request_source
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| /Zephyr-Core-3.7.0/dts/bindings/serial/ |
| D | infineon,xmc4xxx-uart.yaml | 102 simple mapping: in USIC0 interrupt 84->SR0, interrupt 85->SR1, ... etc.
103 In USIC1, interrupt 90->SR0, 91->SR1, etc.
108 The interrupt would map to SR1. From Table "DMA Request Source Selection", request_source
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| /Zephyr-Core-3.7.0/drivers/flash/ |
| D | flash_stm32h7x.c | 166 sr = regs->SR1;
211 while ((FLASH_STM32_REGS(dev)->SR1 & FLASH_SR_QW)
214 while (FLASH_STM32_REGS(dev)->SR1 & FLASH_SR_QW)
243 sector.sr = ®s->SR1;
252 sector.sr = ®s->SR1;
269 sector.sr = ®s->SR1;
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| D | flash_stm32.h | 52 #define SR1 SR macro
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| D | flash_nxp_s32_qspi_nor.c | 452 /* Writing SR1 clears SR2 */ in nxp_s32_qspi_write_status_register()
460 /* buf = [val] or [SR1, val] */ in nxp_s32_qspi_write_status_register()
464 /* Writing SR2 requires writing SR1 as well */ in nxp_s32_qspi_write_status_register()
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| D | nrf_qspi_nor.c | 511 /* Writing sr1 clears sr2. need to read/modify/write both. */ in qspi_wrsr()
523 /* Writing sr2 requires writing sr1 as well. in qspi_wrsr()
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| D | flash_stm32_qspi.c | 998 /* if SR2 write needs SR1 */ in qspi_write_status_register()
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| D | spi_nor.c | 1616 "Need support for lock clear beyond SR1");))
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| D | flash_stm32_xspi.c | 1661 /* if SR2 write needs SR1 */ in stm32_xspi_write_status_register()
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| D | flash_stm32_ospi.c | 1802 /* if SR2 write needs SR1 */ in stm32_ospi_write_status_register()
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| /Zephyr-Core-3.7.0/drivers/usb_c/tcpc/ |
| D | ucpd_stm32.c | 1102 uint32_t sr1; in ucpd_isr() local
1113 sr1 = in ucpd_isr()
1118 } else if (sr1) { in ucpd_isr()
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