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/Zephyr-latest/tests/bsim/bluetooth/ll/edtt/tests_scripts/
Dgatt.llcp.test_list7 GATT/SR/GAC/BV-01-C
8 GATT/SR/GAD/BV-01-C
9 GATT/SR/GAD/BV-02-C
10 GATT/SR/GAD/BV-03-C
11 GATT/SR/GAD/BV-04-C
12 GATT/SR/GAD/BV-05-C
13 GATT/SR/GAD/BV-06-C
14 GATT/SR/GAR/BV-01-C
15 GATT/SR/GAR/BI-01-C
16 GATT/SR/GAR/BI-02-C
[all …]
/Zephyr-latest/arch/arc/core/dsp/
Dswap_dsp_macros.h143 sr r13, [_ARC_V2_DSP_CTRL]
145 sr r13, [_ARC_V2_ACC0_GLO]
147 sr r13, [_ARC_V2_ACC0_GHI]
150 sr r13, [_ARC_V2_DSP_BFLY0]
152 sr r13, [_ARC_V2_DSP_FFT_CTRL]
169 sr r13, [_ARC_V2_AGU_AP0]
171 sr r13, [_ARC_V2_AGU_AP1]
173 sr r13, [_ARC_V2_AGU_AP2]
175 sr r13, [_ARC_V2_AGU_AP3]
177 sr r13, [_ARC_V2_AGU_OS0]
[all …]
/Zephyr-latest/lib/heap/
Dheap_stress.c41 static bool rand_alloc_choice(struct z_heap_stress_rec *sr) in rand_alloc_choice() argument
44 if (sr->blocks_alloced == 0) { in rand_alloc_choice()
46 } else if (sr->blocks_alloced >= sr->nblocks) { in rand_alloc_choice()
65 __ASSERT(sr->total_bytes < 0xffffffffU / 100, "too big for u32!"); in rand_alloc_choice()
66 uint32_t full_pct = (100 * sr->bytes_alloced) / sr->total_bytes; in rand_alloc_choice()
67 uint32_t target = sr->target_percent ? sr->target_percent : 1; in rand_alloc_choice()
70 if (full_pct < sr->target_percent) { in rand_alloc_choice()
81 static size_t rand_alloc_size(struct z_heap_stress_rec *sr) in rand_alloc_size() argument
83 ARG_UNUSED(sr); in rand_alloc_size()
94 static size_t rand_free_choice(struct z_heap_stress_rec *sr) in rand_free_choice() argument
[all …]
/Zephyr-latest/drivers/sdhc/
Dsam_hsmci.c269 uint32_t sr; in sam_hsmci_send_cmd() local
287 sr = hsmci->HSMCI_SR; in sam_hsmci_send_cmd()
291 sr &= ~HSMCI_SR_RCRCE; in sam_hsmci_send_cmd()
294 if ((sr & _HSMCI_SR_ERR) != 0) { in sam_hsmci_send_cmd()
295 LOG_DBG("Status register error bits: %08x", sr & _HSMCI_SR_ERR); in sam_hsmci_send_cmd()
298 } while (!(sr & HSMCI_SR_CMDRDY)); in sam_hsmci_send_cmd()
302 sr = hsmci->HSMCI_SR; in sam_hsmci_send_cmd()
303 } while (!((sr & HSMCI_SR_NOTBUSY) && ((sr & HSMCI_SR_DTIP) == 0))); in sam_hsmci_send_cmd()
316 uint32_t sr = 0; in sam_hsmci_wait_write_end() local
321 sr = hsmci->HSMCI_SR; in sam_hsmci_wait_write_end()
[all …]
/Zephyr-latest/arch/arc/core/
Dreset.S61 sr r0, [_ARC_V2_AUX_IRQ_ACT]
62 sr r0, [_ARC_V2_AUX_IRQ_CTRL]
64 sr r0, [_ARC_V2_AUX_IRQ_HINT]
71 sr r0, [_ARC_V2_IRQ_VECT_BASE_S]
98 sr r2, [_ARC_V2_IC_IVIC]
111 sr r1, [_ARC_V2_DC_IVDC]
134 sr r1, [_ARC_V2_MPU_EN]
144 sr r2, [_ARC_V2_MPU_INDEX]
145 sr r1, [_ARC_V2_MPU_RSTART]
146 sr r1, [_ARC_V2_MPU_REND]
[all …]
Duserspace.S149 sr r0, [_ARC_V2_ERSTATUS]
150 sr r1, [_ARC_V2_ERET]
164 sr r0, [_ARC_V2_ERSEC_STAT]
165 sr r5, [_ARC_V2_SEC_U_SP]
167 sr r5, [_ARC_V2_USER_SP]
228 sr r0,[_ARC_V2_ERSEC_STAT]
231 sr r0,[_ARC_V2_ERSTATUS]
234 sr r0,[_ARC_V2_ERET]
/Zephyr-latest/drivers/wifi/nrf_wifi/inc/
Dcoex_struct.h26 /* Each SR Traffic Info is of type uint32_t */
43 /* To insturct Coexistence Manager to collect and post SR traffic information */
45 /* To insturct Coexistence Manager to allocate a priority window to SR */
49 /* To start allocating periodic priority windows to Wi-Fi and SR */
61 /* To post SR traffic information */
66 * struct coex_collect_sr_traffic_info - Message from CD to CM to request SR traffic info.
70 * Message from CD to CM to request SR traffic information.
101 * @can_be_deferred: activity of Wi-Fi/SR, for which window is requested can be deferred or not.
120 * @sr_window_duration: Indicates duration of SR priority window.
153 * @sr_window_poll_periodicity_vpw: microseconds. This is used to poll through SR window.
[all …]
Dcoex.h33 * Indicates if SR protocol is Bluetooth LE or not.
45 * @brief Function used to configure SR side switch (nRF5340 side switch in nRF7002 DK).
65 * Indicates if SR protocol is Bluetooth LE or not.
/Zephyr-latest/boards/shields/nrf7002ek/doc/
Dindex.rst46 SR Co-existence
49 The nRF7002 EK supports SR co-existence provided the host board supports it. The SR co-existence
53 Two Kconfig options are available to enable SR co-existence:
55 - :kconfig:option:`CONFIG_NRF70_SR_COEX`: Enables SR co-existence driver.
56 - :kconfig:option:`CONFIG_NRF70_SR_COEX_RF_SWITCH`: Control SR side RF switch.
68 - ``nrf7002ek_coex``: Variant for the SR co-existence interface
/Zephyr-latest/include/zephyr/arch/xtensa/
Darch_inlines.h19 * @param sr Name of special register.
23 #define XTENSA_RSR(sr) \ argument
25 __asm__ volatile ("rsr." sr " %0" : "=a"(v)); \
31 * @param sr Name of special register.
34 #define XTENSA_WSR(sr, v) \ argument
36 __asm__ volatile ("wsr." sr " %0" : : "r"(v)); \
/Zephyr-latest/boards/shields/nrf7002eb/doc/
Dindex.rst55 SR Co-existence
58 The nRF7002 EB supports SR co-existence provided the host board supports it. The SR co-existence
61 Two Kconfig options are available to enable SR co-existence:
63 - :kconfig:option:`CONFIG_NRF70_SR_COEX`: Enables SR co-existence.
64 - :kconfig:option:`CONFIG_NRF70_SR_COEX_RF_SWITCH`: Control SR side RF switch.
/Zephyr-latest/arch/arc/include/
Dswap_macros.h114 sr r13, [_ARC_V2_FPU_STATUS]
116 sr r13, [_ARC_V2_FPU_CTRL]
120 sr r13, [_ARC_V2_FPU_DPFP1L]
122 sr r13, [_ARC_V2_FPU_DPFP1H]
124 sr r13, [_ARC_V2_FPU_DPFP2L]
126 sr r13, [_ARC_V2_FPU_DPFP2H]
135 sr r13, [_ARC_V2_SEC_U_SP]
137 sr r13, [_ARC_V2_SEC_K_SP]
140 sr r13, [_ARC_V2_USER_SP]
142 sr r13, [_ARC_V2_KERNEL_SP]
[all …]
/Zephyr-latest/arch/riscv/core/
Disr.S47 RV_E( sr s0, ___callee_saved_t_s0_OFFSET(sp) );\
48 RV_E( sr s1, ___callee_saved_t_s1_OFFSET(sp) );\
49 RV_I( sr s2, ___callee_saved_t_s2_OFFSET(sp) );\
50 RV_I( sr s3, ___callee_saved_t_s3_OFFSET(sp) );\
51 RV_I( sr s4, ___callee_saved_t_s4_OFFSET(sp) );\
52 RV_I( sr s5, ___callee_saved_t_s5_OFFSET(sp) );\
53 RV_I( sr s6, ___callee_saved_t_s6_OFFSET(sp) );\
54 RV_I( sr s7, ___callee_saved_t_s7_OFFSET(sp) );\
55 RV_I( sr s8, ___callee_saved_t_s8_OFFSET(sp) );\
56 RV_I( sr s9, ___callee_saved_t_s9_OFFSET(sp) );\
[all …]
Dreset.S99 sr t1, 0(t0)
101 sr zero, 0(t0)
114 sr t1, 0(t0)
Dswitch.S41 DO_CALLEE_SAVED(sr, a1)
44 sr sp, _thread_offset_to_sp(a1)
47 sr a1, ___thread_t_switch_handle_OFFSET(a1)
/Zephyr-latest/boards/shields/nrf7002eb/boards/
Dnrf54h20dk_nrf54h20_cpuapp.overlay8 * remove this as Wi-Fi SR co-existence is not yet supported on this board.
9 * The external SR RF switch may not even be present on this board.
/Zephyr-latest/drivers/flash/
Dflash_stm32h7x.c62 volatile uint32_t *sr; member
182 uint32_t sr; local
189 sr = regs->ISR;
190 if (sr & (FLASH_FLAG_SNECCERR)) {
197 if (sr & (FLASH_FLAG_DBECCERR)) {
206 if (sr & error_bank) {
211 sr = regs->SR1;
212 if (sr & (FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1)) {
221 if (sr & error_bank1) {
223 LOG_ERR("Status Bank%d: 0x%08x", 1, sr);
[all …]
/Zephyr-latest/dts/bindings/wifi/
Dnordic,nrf70.yaml23 GPIO of the RF Switch to control SR RF output to either SR Antenna
/Zephyr-latest/modules/nrf_wifi/bus/
Dspi_if.c100 uint8_t sr[6]; in spim_read_reg() local
103 .buf = &sr, in spim_read_reg()
104 .len = sizeof(sr), in spim_read_reg()
110 LOG_DBG("err: %d -> %x %x %x %x %x %x", err, sr[0], sr[1], sr[2], sr[3], sr[4], sr[5]); in spim_read_reg()
113 *reg_value = sr[1]; in spim_read_reg()
/Zephyr-latest/drivers/can/
Dcan_sja1000.c385 uint8_t sr; in can_sja1000_send() local
410 sr = can_sja1000_read_reg(dev, CAN_SJA1000_SR); in can_sja1000_send()
411 if ((sr & CAN_SJA1000_SR_TBS) == 0) { in can_sja1000_send()
412 LOG_ERR("transmit buffer locked, sr = 0x%02x", sr); in can_sja1000_send()
485 uint8_t sr; in can_sja1000_recover() local
496 sr = can_sja1000_read_reg(dev, CAN_SJA1000_SR); in can_sja1000_recover()
497 if ((sr & CAN_SJA1000_SR_BS) == 0) { in can_sja1000_recover()
518 while ((sr & CAN_SJA1000_SR_BS) != 0) { in can_sja1000_recover()
524 sr = can_sja1000_read_reg(dev, CAN_SJA1000_SR); in can_sja1000_recover()
574 uint8_t sr; in can_sja1000_handle_receive_irq() local
[all …]
/Zephyr-latest/tests/kernel/fpu_sharing/generic/src/
Dfloat_regs_arc_gcc.h45 "sr %1, [%2];\n\t" in _load_all_float_registers()
47 "sr %1, [%3];\n\t" in _load_all_float_registers()
49 "sr %1, [%4];\n\t" in _load_all_float_registers()
51 "sr %1, [%5];\n\t" in _load_all_float_registers()
/Zephyr-latest/drivers/pwm/
Dpwm_imx.c58 uint32_t cr, sr; in imx_pwm_set_cycles() local
83 sr = PWM_PWMSR_REG(config->base); in imx_pwm_set_cycles()
84 fifoav = PWM_PWMSR_FIFOAV(sr); in imx_pwm_set_cycles()
90 sr = PWM_PWMSR_REG(config->base); in imx_pwm_set_cycles()
91 if (fifoav == PWM_PWMSR_FIFOAV(sr)) { in imx_pwm_set_cycles()
/Zephyr-latest/soc/nordic/common/vpr/
Dsoc_isr_stacking.h96 sr t0, __soc_esf_t_sp_align_OFFSET(t1)
103 sr t2, __struct_arch_esf_mepc_OFFSET(sp)
115 DO_CALLER_SAVED(sr); \
/Zephyr-latest/drivers/timer/
Dwch_systick_ch32v00x.c36 SYSTICK->SR = 0; in ch32v00x_systick_irq()
55 SYSTICK->SR = 0; in ch32v00x_systick_init()
/Zephyr-latest/drivers/usb/device/
Dusb_dc_sam_usbc.c120 static void usb_dc_sam_usbc_isr_sta_dbg(uint32_t ep_idx, uint32_t sr) in usb_dc_sam_usbc_isr_sta_dbg() argument
130 ((sr & USBC_UESTA0_RXSTPI) ? " STP" : "")); in usb_dc_sam_usbc_isr_sta_dbg()
149 #define usb_dc_sam_usbc_isr_sta_dbg(ep_idx, sr) argument
312 uint32_t sr = regs->UESTA[ep_idx]; in usb_dc_ep_isr_sta() local
314 usb_dc_sam_usbc_isr_sta_dbg(ep_idx, sr); in usb_dc_ep_isr_sta()
316 if (sr & USBC_UESTA0_RAMACERI) { in usb_dc_ep_isr_sta()
393 uint32_t sr = regs->UESTA[0]; in usb_dc_ep0_isr() local
401 if (sr & USBC_UESTA0_RXSTPI) { in usb_dc_ep0_isr()
413 if (sr & USBC_UESTA0_RXOUTI) { in usb_dc_ep0_isr()
442 if ((sr & USBC_UESTA0_TXINI) && in usb_dc_ep0_isr()
[all …]

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