| /Zephyr-Core-3.5.0/drivers/spi/ |
| D | Kconfig | 1 # SPI driver configuration options
7 # SPI Drivers
9 menuconfig SPI config
10 bool "Serial Peripheral Interface (SPI) bus drivers"
12 Enable support for the SPI hardware bus.
14 if SPI
34 Enables Driver SPI slave operations. Slave support depends
41 Enables extended operations in the SPI API. Currently, this
44 it would require more features exposed into the SPI buffer.
56 The tolerance value in ms for the SPI completion timeout logic.
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| D | spi_ll_stm32.h | 23 SPI_TypeDef *spi; member
69 static inline uint32_t ll_func_dma_get_reg_addr(SPI_TypeDef *spi, uint32_t location) in ll_func_dma_get_reg_addr() argument
74 return (uint32_t)&(spi->TXDR); in ll_func_dma_get_reg_addr()
77 return (uint32_t)&(spi->RXDR); in ll_func_dma_get_reg_addr()
80 return (uint32_t)LL_SPI_DMA_GetRegAddr(spi); in ll_func_dma_get_reg_addr()
84 /* checks that DMA Tx packet is fully transmitted over the SPI */
85 static inline uint32_t ll_func_spi_dma_busy(SPI_TypeDef *spi) in ll_func_spi_dma_busy() argument
88 return LL_SPI_IsActiveFlag_TXC(spi); in ll_func_spi_dma_busy()
90 /* the SPI Tx empty and busy flags are needed */ in ll_func_spi_dma_busy()
91 return (LL_SPI_IsActiveFlag_TXE(spi) && in ll_func_spi_dma_busy()
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| D | Kconfig.sam | 1 # Atmel SAM SPI
8 bool "Atmel SAM series SPI driver"
13 Enable support for the SAM SPI driver.
17 bool "SPI SAM DMA Support"
20 Enable using DMA with SPI for SPI instances that enable dma channels in
26 default 8 # Sensible default that covers most common spi transactions
28 When RTIO is use with SPI each driver holds a context with which blocking
29 API calls use to perform SPI transactions. This queue needs to be as deep
30 as the longest set of spi_buf_sets used, where normal SPI operations are
32 spi buffer sets for transmit/receive are not always matched equally in
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| D | Kconfig.xmc4xxx | 5 bool "XMC4XX SPI driver"
10 Enable XMC4XXX SPI driver.
16 bool "XMC4XXX SPI interrupt mode"
18 Enables interrupt support for XMC4XXX SPI driver.
21 bool "XMC4XXX SPI DMA support"
24 Enables DMA for SPI transfers.
29 int "Timeout in milliseconds for an SPI transaction to complete if using DMA"
32 Sets timeout in milliseconds for an SPI transaction to complete when using DMA.
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| D | Kconfig.stm32 | 1 # STM32 SPI driver configuration options
7 bool "STM32 MCU SPI controller driver"
12 Enable SPI support on the STM32 family of processors.
17 bool "STM32 MCU SPI Interrupt Support"
19 Enable Interrupt support for the SPI Driver of STM32 family.
22 bool "STM32 MCU SPI DMA Support"
26 Enable the SPI DMA mode for SPI instances
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| D | spi_pw.c | 12 #include <zephyr/drivers/spi.h>
44 static bool is_spi_transfer_ongoing(struct spi_pw_data *spi) in is_spi_transfer_ongoing() argument
46 return spi_context_tx_on(&spi->ctx) || spi_context_rx_on(&spi->ctx); in is_spi_transfer_ongoing()
145 struct spi_pw_data *spi = dev->data; in spi_pw_cs_ctrl_enable() local
148 if (spi->cs_mode == CS_SW_MODE) { in spi_pw_cs_ctrl_enable()
150 } else if (spi->cs_mode == CS_GPIO_MODE) { in spi_pw_cs_ctrl_enable()
151 spi_context_cs_control(&spi->ctx, true); in spi_pw_cs_ctrl_enable()
154 if (spi->cs_mode == CS_SW_MODE) { in spi_pw_cs_ctrl_enable()
156 } else if (spi->cs_mode == CS_GPIO_MODE) { in spi_pw_cs_ctrl_enable()
157 spi_context_cs_control(&spi->ctx, false); in spi_pw_cs_ctrl_enable()
[all …]
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| D | spi_dw.c | 10 /* spi_dw.c - Designware SPI driver implementation */
45 #include <zephyr/drivers/spi.h>
55 static inline bool spi_dw_is_slave(struct spi_dw_data *spi) in spi_dw_is_slave() argument
58 spi_context_is_slave(&spi->ctx)); in spi_dw_is_slave()
64 struct spi_dw_data *spi = dev->data; in completed() local
70 if (spi_context_tx_on(&spi->ctx) || in completed()
71 spi_context_rx_on(&spi->ctx)) { in completed()
85 spi_context_cs_control(&spi->ctx, false); in completed()
87 LOG_DBG("SPI transaction completed %s error", in completed()
90 spi_context_complete(&spi->ctx, dev, error); in completed()
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| /Zephyr-Core-3.5.0/tests/drivers/spi/spi_loopback/ |
| D | testcase.yaml | 2 depends_on: spi
5 - spi
7 filter: dt_compat_enabled("test-spi-loopback-slow") and
8 dt_compat_enabled("test-spi-loopback-fast")
13 drivers.spi.loopback: {}
14 drivers.spi.loopback.internal:
16 drivers.spi.loopback.lpspi.dma:
20 drivers.spi.loopback.lpspi.async.unset:
25 drivers.spi.loopback.lpspi.dma.async.unset:
30 drivers.spi.loopback.rtio:
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| /Zephyr-Core-3.5.0/soc/arm/microchip_mec/ |
| D | Kconfig | 21 which generates an SPI image with TAG, Header, and firmware binary. This
23 Boot-ROM. Use the full Microchip SPI image generator program for
35 prompt "Clock rate to use for SPI flash"
38 This selects the SPI clock frequency that will be used for loading
42 bool "SPI flash clock rate of 12 MHz"
45 bool "SPI flash clock rate of 16 MHz"
48 bool "SPI flash clock rate of 24 MHz"
51 bool "SPI flash clock rate of 48 MHz"
63 prompt "Reading mode used by the SPI flash"
66 This sets the reading mode that can be used by the SPI flash.
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| /Zephyr-Core-3.5.0/dts/bindings/led_strip/ |
| D | worldsemi,ws2812-spi.yaml | 5 Worldsemi WS2812 LED strip, SPI binding
8 strip with a SPI master.
10 The SPI driver should be usable as long as a zephyr SPI API driver
14 - spi-max-frequency
15 - spi-zero-frame
16 - spi-one-frame.
21 compatible: "worldsemi,ws2812-spi"
23 include: [spi-device.yaml, ws2812.yaml]
27 spi-cpol:
29 description: Set SPI clock polarity.
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| /Zephyr-Core-3.5.0/include/zephyr/devicetree/ |
| D | spi.h | 3 * @brief SPI Devicetree macro public API header file.
20 * @defgroup devicetree-spi Devicetree SPI API
26 * @brief Does a SPI controller node have chip select GPIOs configured?
28 * SPI bus controllers use the "cs-gpios" property for configuring
34 * spi1: spi@... {
35 * compatible = "vnd,spi";
40 * spi2: spi@... {
41 * compatible = "vnd,spi";
49 * @param spi a SPI bus controller node identifier
50 * @return 1 if "spi" has a cs-gpios property, 0 otherwise
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| /Zephyr-Core-3.5.0/soc/arm/nuvoton_npcx/ |
| D | Kconfig | 49 prompt "Clock rate to use for SPI flash"
56 bool "SPI flash max clock rate of 20 MHz"
59 bool "SPI flash max clock rate of 25 MHz"
62 bool "SPI flash max clock rate of 33 MHz"
66 bool "SPI flash max clock rate of 40 MHz"
69 bool "SPI flash max clock rate of 50 MHz"
81 prompt "Reading mode used by the SPI flash"
84 This sets the reading mode that can be used by the SPI flash.
88 bool "SPI flash operates with normal reading mode"
91 bool "SPI flash operates with fast reading mode"
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| /Zephyr-Core-3.5.0/samples/drivers/spi_flash_at45/ |
| D | sample.yaml | 2 name: SPI Flash AT45 Sample
4 sample.drivers.spi.flash.at45.build:
6 - spi
8 depends_on: spi
11 sample.drivers.spi.flash.at45.build.page_layout:
14 - spi
16 depends_on: spi
19 sample.drivers.spi.flash.at45.build.pm:
22 - spi
24 depends_on: spi
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| /Zephyr-Core-3.5.0/subsys/mgmt/ec_host_cmd/backends/ |
| D | ec_host_cmd_backend_spi_stm32.c | 7 /* The SPI STM32 backend implements dedicated SPI driver for Host Commands. Unfortunately, the
8 * current SPI API can't be used to handle the host commands communication. The main issues are
9 * unknown command size sent by the host (the SPI transaction sends/receives specific number of
10 * bytes) and need to constant sending status byte (the SPI module is enabled and disabled per
22 #include <zephyr/drivers/spi.h>
28 /* The default compatible string of a SPI devicetree node has to be replaced with the one
29 * dedicated for Host Commands. It disabled standard SPI driver. For STM32 SPI "st,stm32-spi" has
30 * to be changed to "st,stm32-spi-host-cmd". The remaining "additional" compatible strings should
35 "The chosen backend node is obligatory for SPI STM32 backend.");
38 "Invalid compatible of the chosen spi node.");
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| /Zephyr-Core-3.5.0/samples/drivers/spi_flash/ |
| D | sample.yaml | 2 name: SPI Flash Sample
4 sample.drivers.spi.flash:
6 - spi
8 filter: dt_compat_enabled("jedec,spi-nor") or dt_compat_enabled("st,stm32-qspi-nor")
21 depends_on: spi
22 sample.drivers.spi.flash_dpd:
24 - spi
26 filter: dt_compat_enabled("jedec,spi-nor")
31 depends_on: spi
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| /Zephyr-Core-3.5.0/dts/bindings/spi/ |
| D | nordic,nrf-spi-common.yaml | 4 # Common fields for Nordic nRF family SPI peripherals
6 include: [spi-controller.yaml, pinctrl-device.yaml]
22 Maximum data rate the SPI peripheral can be driven at, in Hz. This
31 (line high), the most common value used in SPI transfers.
43 Optional bi-directional line that allows SPI master to indicate to SPI
49 - initially, SPI slave configures its WAKE line pin as an input and SPI
51 - when a transfer is to be performed, SPI master configures its WAKE
53 high but allows SPI slave to override that state
54 - when SPI slave detects the high state of the WAKE line, it prepares
58 to SPI master that it can proceed with the transfer
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| D | spi-controller.yaml | 4 # Common fields for SPI controllers
8 bus: spi
14 Clock frequency the SPI peripheral is being driven at, in Hz.
30 spi@... {
35 spi-device@0 {
39 spi-device@1 {
46 The child node "spi-device@0" specifies a SPI device with
48 GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
58 SPI controllers with dedicated CS pins do not need to define
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| /Zephyr-Core-3.5.0/tests/drivers/build_all/sensor/ |
| D | spi.dtsi | 6 * Application overlay for spi devices
16 spi-max-frequency = <0>;
23 spi-max-frequency = <0>;
30 spi-max-frequency = <0>;
36 spi-max-frequency = <0>;
43 spi-max-frequency = <0>;
49 spi-max-frequency = <0>;
56 spi-max-frequency = <0>;
63 spi-max-frequency = <0>;
70 spi-max-frequency = <0>;
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| /Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/common/ |
| D | Kconfig.soc | 16 bool "Support for external, SPI-connected RAM"
18 This enables support for an external SPI RAM chip, connected in
19 parallel with the main SPI flash chip.
48 menu "SPI RAM config"
52 prompt "Mode (QUAD/OCT) of SPI RAM chip in use"
61 prompt "Type of SPI RAM chip in use"
90 Select the speed for the SPI RAM chip.
91 If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now:
93 1. Flash SPI running at 40MHz and RAM SPI running at 40MHz
94 2. Flash SPI running at 80MHz and RAM SPI running at 40MHz
[all …]
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| /Zephyr-Core-3.5.0/doc/services/device_mgmt/ |
| D | ec_host_cmd.rst | 39 Another case is SPI. Unfortunately, the current SPI API can't be used to handle the host commands
40 communication. The main issues are unknown command size sent by the host (the SPI transaction
41 sends/receives specific number of bytes) and need to constant sending status byte (the SPI module
42 is enabled and disabled per transaction). It forces implementing the SPI driver within a backend,
43 as it is done for SHI. That means a SPI backend has to be implemented per chip family. However, it
44 can be changed in the future once the SPI API is extended to host command needs. Please check `the
47 That approach requires configuring the SPI dts node in a special way. The main compatible string of
48 a SPI node has changed to use the Host Command version of a SPI driver. The rest of the properties
49 should be configured as usual. Example of the SPI node for STM32:
55 * STM32 SPI driver
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| /Zephyr-Core-3.5.0/drivers/sensor/icm42605/ |
| D | icm42605_setup.c | 23 result = inv_spi_read(&cfg->spi, REG_ACCEL_CONFIG0, &databuf, 1); in icm42605_set_fs()
31 result = inv_spi_single_write(&cfg->spi, REG_ACCEL_CONFIG0, &databuf); in icm42605_set_fs()
33 result = inv_spi_read(&cfg->spi, REG_GYRO_CONFIG0, &databuf, 1); in icm42605_set_fs()
42 result = inv_spi_single_write(&cfg->spi, REG_GYRO_CONFIG0, &databuf); in icm42605_set_fs()
63 result = inv_spi_read(&cfg->spi, REG_ACCEL_CONFIG0, &databuf, 1); in icm42605_set_odr()
99 result = inv_spi_single_write(&cfg->spi, REG_ACCEL_CONFIG0, &databuf); in icm42605_set_odr()
107 result = inv_spi_read(&cfg->spi, REG_GYRO_CONFIG0, &databuf, 1); in icm42605_set_odr()
139 result = inv_spi_single_write(&cfg->spi, REG_GYRO_CONFIG0, &databuf); in icm42605_set_odr()
153 result = inv_spi_read(&cfg->spi, REG_WHO_AM_I, &v, 1); in icm42605_sensor_init()
161 result = inv_spi_read(&cfg->spi, REG_DEVICE_CONFIG, &v, 1); in icm42605_sensor_init()
[all …]
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| /Zephyr-Core-3.5.0/tests/drivers/spi/dt_spec/ |
| D | app.overlay | 22 test_spi_cs: spi@33334444 {
25 compatible = "vnd,spi";
32 test_spi_dev_cs: test-spi-dev@0 {
33 compatible = "vnd,spi-device";
35 spi-max-frequency = <2000000>;
39 test_spi_no_cs: spi@55556666 {
42 compatible = "vnd,spi";
47 test_spi_dev_no_cs: test-spi-dev@0 {
48 compatible = "vnd,spi-device";
50 spi-max-frequency = <2000000>;
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| /Zephyr-Core-3.5.0/dts/bindings/bluetooth/ |
| D | zephyr,bt-hci-spi-slave.yaml | 5 Configures SPI slave settings for a Bluetooth controller that uses
6 Zephyr's Bluetooth Host Controller Interface SPI (HCI SPI) driver.
12 compatible = "zephyr,bt-hci-spi-slave";
18 The bt-hci@0 node configures an HCI SPI slave on SPI slave
25 compatible: "zephyr,bt-hci-spi-slave"
29 on-bus: spi
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| /Zephyr-Core-3.5.0/dts/bindings/net/wireless/ |
| D | nordic,nrf21540-fem.yaml | 8 See the "nordic,nrf21540-fem-spi" binding to configure the SPI
9 interface. The SPI interface should be configured as a child node
10 of the SPI bus you have connected to the FEM. Then you "connect"
11 the FEM and SPI configurations using the spi-if property.
13 Here is an example nRF21540 configuration with a SPI interface
22 my_spi_if: nrf21540-spi@0 {
23 compatible = "nordic,nrf21540-fem-spi";
25 spi-max-frequency = <8000000>;
33 spi-if = <&my_spi_if>;
48 - SPI communication via SPIM0 (the bus, or parent node, of
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| /Zephyr-Core-3.5.0/samples/bluetooth/hci_spi/ |
| D | README.rst | 1 .. _bluetooth-hci-spi-sample:
3 Bluetooth: HCI SPI
9 Expose Zephyr Bluetooth Controller support over SPI to another device/CPU using
10 the Zephyr SPI HCI transport protocol (similar to BlueNRG).
15 A board with SPI slave, GPIO and Bluetooth Low Energy support.
21 for the HCI SPI slave device with compatible
22 :dtcompatible:`zephyr,bt-hci-spi-slave`. This node sets an interrupt line to
23 the host and associates the application with a SPI bus to use.
33 You will also need a separate chip acting as BT HCI SPI master. This
34 application is compatible with the HCI SPI master driver provided by
|
