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/Zephyr-latest/dts/bindings/memory-controllers/
Datmel,sam-smc.yaml5 Atmel Static Memory Controller (SMC).
7 The SMC allows to interface with static-memory mapped external devices such as
10 The SMC is clocked through the Master Clock (MCK) which is controlled by the
13 The SMC controller can have up to 4 children defining the connected external
17 &smc {
25 atmel,smc-write-mode = "nwe";
26 atmel,smc-read-mode = "nrd";
27 atmel,smc-setup-timing = <1 1 1 1>;
28 atmel,smc-pulse-timing = <6 6 6 6>;
29 atmel,smc-cycle-timing = <7 7>;
[all …]
/Zephyr-latest/include/zephyr/drivers/sip_svc/
Dsip_svc_agilex_smc.h13 * SMC protocol.
16 /* @brief SMC return status
26 /* @brief SMC Intel Header at a1
50 /* @brief SYNC SMC Function IDs
60 /* @brief ASYNC SMC Function IDs
Dsip_svc_proto.h16 * when requesting SMC/HVC service via 'send' function.
18 * Service to fill in the SMC/HVC return value in struct sip_svc_response
62 * return the result immediately during SMC/HVC call.
66 * separate SMC/HVC call. Use this method if the request requires longer
80 * - Unrecognized SMC/HVC Function ID.
116 * SMC/HVC
158 * - SMC/HVC return value
/Zephyr-latest/dts/bindings/sip_svc/
Dintel,agilex-socfpga-sip-smc.yaml5 description: SiP SVC driver instance on Intel Agilex SOC FPGA for SMC call
7 compatible: "intel,socfpga-agilex-sip-smc"
14 const: smc
/Zephyr-latest/tests/arch/arm64/arm64_smc_call/src/
Dmain.c10 /* SMC function IDs for Standard Service queries */
34 zassert_true(res.a0 > 0, "Wrong smc call count"); in ZTEST()
38 "Wrong smc call version"); in ZTEST()
41 zassert_true(res.a0 == SMC_UNK, "Wrong return code from smc call"); in ZTEST()
/Zephyr-latest/tests/arch/arm64/arm64_smc_call/
Dtestcase.yaml2 arch.arm64.smc_call.smc:
6 - smc
DKconfig5 bool "Set smc call method to hvc"
/Zephyr-latest/boards/atmel/sam/sam4s_xplained/
Dsam4s_xplained.dts215 &smc {
223 atmel,smc-write-mode = "nwe";
224 atmel,smc-read-mode = "nrd";
225 atmel,smc-setup-timing = <1 1 1 1>;
226 atmel,smc-pulse-timing = <6 6 6 6>;
227 atmel,smc-cycle-timing = <7 7>;
233 atmel,smc-write-mode = "nwe";
234 atmel,smc-read-mode = "nrd";
235 atmel,smc-setup-timing = <1 1 1 1>;
236 atmel,smc-pulse-timing = <6 6 6 6>;
[all …]
/Zephyr-latest/arch/arm64/core/
Dsmccc-call.S9 * Monitor Call (SMC) and Hypervisor Call (HVC).
30 * The SMC instruction is used to generate a synchronous exception that is
35 SMCCC smc
/Zephyr-latest/drivers/fpga/
Dfpga_altera_agilex_bridge.h160 /* SMC COMMAND ID to disable all the bridges */
162 /* SMC COMMAND ID to enable all the bridges */
164 /* SMC Cancel Command */
166 /* SMC COMMAND ID to check Reconfig status to SDM via mailbox */
168 /* SMC COMMAND ID to check Reconfig status to SDM via mailbox */
190 /* SMC request parameter a2 index*/
192 /* SMC request parameter a3 index */
/Zephyr-latest/drivers/tee/optee/
Doptee_smc.h12 * world and normal world kernel driver. We're following ARM SMC Calling
16 * This file depends on optee_msg.h being included to expand the SMC id
61 * Function specified by SMC Calling convention.
82 * Function specified by SMC Calling convention
96 * Function specified by SMC Calling convention
153 * a0 SMC Function ID, OPTEE_SMC_CALL_WITH_ARG or OPTEE_SMC_CALL_WITH_RPC_ARG
162 * a0 SMC Function ID, OPTEE_SMC_CALL_WITH_REGD_ARG
213 * a0 SMC Function ID, OPTEE_SMC_GET_SHM_CONFIG
241 * a0 SMC Function ID, OPTEE_SMC_L2CC_MUTEX
280 * a0 SMC Function ID, OPTEE_SMC_EXCHANGE_CAPABILITIES
[all …]
/Zephyr-latest/tests/drivers/build_all/fpga/
Dapp.overlay47 sip_smc: smc {
48 compatible = "intel,socfpga-agilex-sip-smc";
49 method = "smc";
/Zephyr-latest/include/zephyr/sip_svc/
Dsip_svc.h15 * SMC/HVC call from kernel running at EL1 to hypervisor/secure
18 * Only allow one SMC and one HVC per system.
26 * The service will return the SMC/HVC return value to the client
69 * @param ctrl Pointer to controller instance whose service provides ARM SMC/HVC
101 * SMC/HVC to hypervisor/secure monitor firmware running at EL2/EL3.
138 * @brief Client requests to send a SMC/HVC call to EL3/EL2
149 * @param cb Callback. SMC/SVC return value will be passed to client via
/Zephyr-latest/soc/nxp/kinetis/kv5x/
Dsoc.c87 SMC->PMPROT |= SMC_PMPROT_AHSRUN_MASK; in soc_early_init_hook()
88 SMC->PMCTRL = (SMC->PMCTRL & ~SMC_PMCTRL_RUNM_MASK) | in soc_early_init_hook()
/Zephyr-latest/include/zephyr/arch/arm64/
Darm-smccc.h11 * Result from SMC/HVC call
47 * @brief Make SMC calls
/Zephyr-latest/soc/nxp/kinetis/ke1xf/
Dpower.c36 SMC->STOPCTRL = SMC_STOPCTRL_PSTOPO(substate_id); in pm_state_set()
44 if (SMC->PMCTRL & SMC_PMCTRL_STOPA_MASK) { in pm_state_set()
/Zephyr-latest/soc/nxp/kinetis/ke1xz/
Dpower.c34 SMC->STOPCTRL = SMC_STOPCTRL_PSTOPO(substate_id); in pm_state_set()
41 if (SMC->PMCTRL & SMC_PMCTRL_STOPA_MASK) { in pm_state_set()
/Zephyr-latest/drivers/memc/
Dmemc_sam_smc.c26 Smc *regs;
39 /* Enable SMC clock in PMC */ in memc_smc_init()
96 .regs = (Smc *)DT_INST_REG_ADDR(inst), \
DKconfig.sam5 bool "Atmel Static Memory Controller (SMC)"
/Zephyr-latest/tests/drivers/tee/optee/boards/
Dnative_sim_64.overlay9 method = "smc";
/Zephyr-latest/dts/bindings/arm/
Dlinaro,optee-tz.yaml16 - smc
/Zephyr-latest/dts/bindings/pm_cpu_ops/
Darm_psci.yaml17 - smc
/Zephyr-latest/soc/nxp/kinetis/k6x/
Dsoc.c158 SMC->PMPROT |= SMC_PMPROT_AHSRUN_MASK; in soc_early_init_hook()
159 SMC->PMCTRL = (SMC->PMCTRL & ~SMC_PMCTRL_RUNM_MASK) | in soc_early_init_hook()
/Zephyr-latest/drivers/sip_svc/
Dsip_smc_intel_socfpga.c35 /* Synchronous SMC Function IDs */ in intel_sip_smc_plat_func_id_valid()
50 /* Asynchronous SMC Function IDs */ in intel_sip_smc_plat_func_id_valid()
93 /* Assign the trans id into intel smc header a1 */ in intel_sip_smc_plat_update_trans_id()
124 /* Fill in SMC parameter to read mailbox response */ in intel_sip_smc_plat_async_res_req()
DKconfig.sip_smc_agilex10 Support for SDM mailbox fifo in Intel SoC FPGA Agilex via SMC calls.

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