Home
last modified time | relevance | path

Searched full:s3 (Results 1 – 25 of 61) sorted by relevance

123

/Zephyr-Core-3.5.0/.github/workflows/
Ddoc-publish.yml43 - name: Upload to AWS S3
53 aws s3 sync --quiet html-output/html s3://docs.zephyrproject.org/${VERSION} --delete
54 …aws s3 sync --quiet html-output/html/doxygen/html s3://docs.zephyrproject.org/apidoc/${VERSION} --…
55 aws s3 cp --quiet pdf-output/zephyr.pdf s3://docs.zephyrproject.org/${VERSION}/zephyr.pdf
Ddaily_test_version.yml35 - name: Upload to AWS S3
38 aws s3 cp versions.json s3://testing.zephyrproject.org/daily_tests/versions.json
Dbug_snapshot.yaml5 # using xz. Upload the xz file to Amazon S3.
51 - name: Upload to AWS S3
63 PUBLISH_UPLOAD_URI="s3://${PUBLISH_BUCKET}/${PUBLISH_ROOT}/${BUGS_PICKLE_FILENAME}"
66 aws s3 cp --quiet ${BUGS_PICKLE_PATH} ${PUBLISH_UPLOAD_URI}
Ddoc-publish-pr.yml57 - name: Upload to AWS S3
61 aws s3 sync --quiet html-output/html \
62 s3://builds.zephyrproject.org/${{ github.event.repository.name }}/pr/${PR_NUM}/docs \
Dissue_count.yml54 …aws s3 cp --quiet IssuesReport.html s3://testing.zephyrproject.org/issues/$GITHUB_REPOSITORY/index…
/Zephyr-Core-3.5.0/drivers/fpga/
DKconfig.eos_s31 # FPGA EOS S3 driver configuration options
7 bool "EOS S3 fpga driver"
9 Enable EOS S3 FPGA driver.
/Zephyr-Core-3.5.0/dts/bindings/pinctrl/
Dquicklogic,eos-s3-pinctrl.yaml5 Quicklogic EOS S3 IO MUX binding covers the 46 IOMUX_PAD_x_CTRL registers
13 #include <dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h>
26 compatible: "quicklogic,eos-s3-pinctrl"
54 Quicklogic EOS S3 pin's configuration (pin, IO function).
/Zephyr-Core-3.5.0/dts/bindings/gpio/
Dquicklogic,eos-s3-gpio.yaml1 description: EOS S3 GPIO node
3 compatible: "quicklogic,eos-s3-gpio"
19 a primary(0) or a secondary(1) pin. EOS S3 supports up to 8 GPIOs
/Zephyr-Core-3.5.0/drivers/pinctrl/
DKconfig.eos_s35 bool "QuickLogic EOS S3 SoC pinctrl driver"
9 Enable driver for the QuickLogic EOS S3 SoC pinctrl driver
/Zephyr-Core-3.5.0/boards/xtensa/esp32s3_devkitm/doc/
Dindex.rst9 The ESP32-S3-DevKitM is an entry-level development board equipped with either ESP32-S3-MINI-1
10 or ESP32-S3-MINI-1U, a module named for its small size. This board integrates complete Wi-Fi
11 and Bluetooth Low Energy functions. For more information, check `ESP32-S3 DevKitM`_
16 ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi
21 ESP32-S3 DevKitM includes the following features:
77 ESP32S3-DevKitM allows 2 different applications to be executed in ESP32-S3 SoC. Due to its dual-core
81 For more information, check the datasheet at `ESP32-S3 Datasheet`_.
86 Current Zephyr's ESP32-S3-DevKitM board supports the following features:
255 ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0.
258 ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB…
[all …]
/Zephyr-Core-3.5.0/scripts/coccinelle/
Dderef_null.cocci56 statement S1,S2,S3,S4;
89 else S3
117 statement S1,S2,S3,S4;
149 else S3
177 statement S1,S2,S3,S4;
210 else S3
250 statement S1,S2,S3,S4;
282 else S3
/Zephyr-Core-3.5.0/samples/boards/qomu/
DREADME.rst6 This sample demonstrates how to load bitstream on EOS-S3 FPGA and use the
12 * `QuickLogic Qomu board <https://www.quicklogic.com/products/eos-s3/quickfeather-development-kit/>…
/Zephyr-Core-3.5.0/boards/xtensa/esp32s3_devkitm/support/
Dopenocd.cfg6 # Source the ESP32-S3 configuration file
/Zephyr-Core-3.5.0/boards/xtensa/xiao_esp32s3/support/
Dopenocd.cfg6 # Source the ESP32-S3 configuration file
/Zephyr-Core-3.5.0/boards/xtensa/esp32s3_luatos_core/support/
Dopenocd.cfg6 # Source the ESP32-S3 configuration file
/Zephyr-Core-3.5.0/soc/arm/quicklogic_eos_s3/
DKconfig.soc5 bool "QuickLogic EOS S3 SoC"
/Zephyr-Core-3.5.0/drivers/gpio/
DKconfig.eos_s311 Enable the EOS S3 gpio driver.
/Zephyr-Core-3.5.0/boards/xtensa/esp32s3_luatos_core/doc/
Dindex.rst9 The ESP32S3-LUATOS-CORE development board is a compact board based on Espressif ESP32-S3.
20 ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi
78 For more information, check the datasheet at `ESP32-S3 Datasheet`_.
261 ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0.
264 ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB…
267 for ESP32-S3`_.
283 .. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/ap…
291 .. _ESP32-S3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1…
/Zephyr-Core-3.5.0/boards/xtensa/esp32s3_devkitm/
Desp32s3_devkitm.yaml2 name: ESP32-S3 DevKitM
/Zephyr-Core-3.5.0/boards/xtensa/esp32s3_luatos_core/
Desp32s3_luatos_core.yaml2 name: ESP32-S3 Core
Desp32s3_luatos_core_usb.yaml2 name: ESP32-S3 Core USB
/Zephyr-Core-3.5.0/dts/arm/quicklogic/
Dquicklogic_eos_s3.dtsi58 compatible = "quicklogic,eos-s3-gpio";
69 compatible = "quicklogic,eos-s3-pinctrl";
/Zephyr-Core-3.5.0/samples/subsys/zbus/benchmark/src/
Dbenchmark.c42 s3, s4
65 ZBUS_SUBSCRIBER_DEFINE(s3, 4);
109 S_TASK(s3) in S_TASK()
139 ZBUS_LISTENER_DEFINE(s3, s_cb);
/Zephyr-Core-3.5.0/boards/arm/qomu/doc/
Dindex.rst9 The Qomu board is a platform with an on-board QuickLogic EOS S3 Sensor Processing Platform.
21 - QuickLogic EOS S3 MCU Platform
/Zephyr-Core-3.5.0/boards/xtensa/xiao_esp32s3/doc/
Dindex.rst10 Espressif ESP32-S3 WiFi/Bluetooth dual-mode chip.
23 This board is based on the ESP32-S3 with 8MB of flash, WiFi and BLE support. It
28 ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi
214 ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0.
217 ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB…
220 for ESP32-S3`_.
235 .. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/ap…

123