Searched full:processor (Results 1 – 25 of 679) sorted by relevance
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| /Zephyr-latest/include/zephyr/drivers/misc/ft8xx/ |
| D | ft8xx_copro.h | 22 * @brief FT8xx co-processor engine functions
23 * @defgroup ft8xx_copro FT8xx co-processor
28 /** Co-processor widget is drawn in 3D effect */
30 /** Co-processor option to decode the JPEG image to RGB565 format */
32 /** Co-processor option to decode the JPEG image to L8 format, i.e., monochrome */
36 /** Co-processor widget is drawn without 3D effect */
40 /** Co-processor widget centers horizontally */
42 /** Co-processor widget centers vertically */
44 /** Co-processor widget centers horizontally and vertically */
48 /** Co-processor widget has no background drawn */
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| /Zephyr-latest/boards/intel/rpl/doc/ |
| D | index.rst | 8 Raptor Lake processor is a 13th generation 64-bit multi-core processor built
12 Raptor Lake S and Raptor Lake P processor lines are supported.
14 The S-Processor line is a 2-Chip Platform that includes the Processor Die and
17 The P-Processor line is a 2-Die Multi Chip Package (MCP) that includes the
18 Processor Die and Platform Controller Hub (PCH-P) Die on the same package as
19 the Processor Die.
21 For more information about Raptor Lake Processor lines, P-cores, and E-cores
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| /Zephyr-latest/samples/net/openthread/coprocessor/ |
| D | README.rst | 2 :name: OpenThread co-processor
5 Build a Thread border-router using OpenThread's co-processor designs.
10 OpenThread Co-Processor allows building a Thread Border Router. The code in this
12 The Co-Processor can act in two variants: Network Co-Processor (NCP) and Radio
13 Co-Processor (RCP), see https://openthread.io/platforms/co-processor.
19 The preferred Co-Processor configuration of OpenThread is RCP now.
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| /Zephyr-latest/drivers/gpio/ |
| D | Kconfig.xlnx_ps | 2 # Xilinx Processor System MIO / EMIO GPIO controller driver
10 bool "Xilinx Processor System MIO / EMIO GPIO controller driver"
15 Enable the Xilinx Processor System MIO / EMIO GPIO controller driver.
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| /Zephyr-latest/boards/intel/niosv_g/doc/ |
| D | index.rst | 13 Nios® V/g Processor Intel® FPGA IP
23 For example, Arria10 Nios® V/g processor example design system prebuilt files can be downloaded fro…
24 …t/www/us/en/design-example/776196/intel-arria-10-fpga-hello-world-design-on-nios-v-g-processor.html
28 Create Nios® V/g processor example design system in FPGA
31 Please use Intel Quartus Programmer tool to program Nios® V/g processor based system into the FPGA …
33 In order to create the Nios® V/g processor inside the FPGA device, please download the generated .s…
44 top.sof is referring to Nios® V/m processor based system SRAM Object File.
55 Use the JTAG UART terminal to print the stdout and stderr of the Nios® V/g processor system.
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| /Zephyr-latest/boards/intel/adl/doc/ |
| D | index.rst | 8 Alder Lake processor is a 64-bit multi-core processor built on 10-nanometer
11 Currently supported is N-processor line, Single Chip Platform that consists of
12 the Processor Die and Alder Lake N Platform Controller Hub (ADL-N PCH) Die on
15 Proposed branding for Adler Lake N is Intel Processor (N100,N200) and
65 .. _INTEL_ADL: https://edc.intel.com/content/www/us/en/design/products/platforms/processor-and-core…
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| /Zephyr-latest/boards/intel/niosv_m/doc/ |
| D | index.rst | 13 Nios® V/m Processor Intel® FPGA IP
23 For example, Arria10 Nios® V/m processor example design system prebuilt files can be downloaded fro…
28 Create Nios® V/m processor example design system in FPGA
31 Please use Intel Quartus Programmer tool to program Nios® V/m processor based system into the FPGA …
33 In order to create the Nios® V/m processor inside the FPGA device, please download the generated .s…
44 top.sof is referring to Nios® V/m processor based system SRAM Object File.
55 Use the JTAG UART terminal to print the stdout and stderr of the Nios® V/m processor system.
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| /Zephyr-latest/doc/hardware/peripherals/ |
| D | peci.rst | 11 The PECI interface allows external devices to read processor temperature,
12 perform processor manageability functions, and manage processor interface
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| /Zephyr-latest/arch/sparc/core/ |
| D | sw_trap_set_pil.S | 14 * Set processor interrupt level
23 * - %i0: New processor interrupt level
26 * - %i0: Old processor interrupt level
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| /Zephyr-latest/boards/renesas/rcar_salvator_x/support/ |
| D | openocd.cfg | 39 # This function make use of A5x processor to:
42 # - Halt the processor
63 # resume a5x processor or cmt timer will not run
65 # set CR7 processor as default target for future commands
72 # Resume the A57 processor and gives
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| /Zephyr-latest/samples/subsys/ipc/ |
| D | ipc.rst | 2 :name: Inter-Processor Communication (IPC)
6 Samples that demonstrate :ref:`Inter-Processor Communication (IPC) <ipc_service>` features.
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| /Zephyr-latest/drivers/pinctrl/ |
| D | Kconfig.xlnx | 5 bool "Xilinx Zynq 7000 processor system MIO pin controller driver"
10 Enable the Xilinx Zynq 7000 processor system MIO pin controller driver.
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| /Zephyr-latest/soc/intel/intel_niosv/niosv/ |
| D | Kconfig | 19 Intel FPGA NIOSV Microcontroller Core Processor
24 Intel FPGA NIOSV General Purpose Processor
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| D | Kconfig.soc | 18 Intel FPGA NIOSV Microcontroller Core Processor
24 Intel FPGA NIOSV General Purpose Processor
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| /Zephyr-latest/soc/atmel/sam/sam3x/ |
| D | soc.c | 15 * for the Atmel SAM3X series processor.
25 * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
78 * With Processor Clock prescaler at 1 in clock_init()
79 * Processor Clock (HCLK) = 84 MHz. in clock_init()
105 * keep Processor Clock (HCLK) and thus be able to debug in soc_reset_hook()
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| /Zephyr-latest/subsys/net/l2/openthread/ |
| D | Kconfig | 214 bool "OpenThread Co-Processor"
219 Enable Co-Processor in OpenThread stack.
224 prompt "OpenThread Co-Processor type"
226 This option selects Thread network co-processor type
229 bool "NCP - Network Co-Processor"
231 bool "RCP - Radio Co-Processor"
235 int "Set Co-Processor UART ring buffer size"
238 TX buffer size for the OpenThread Co-Processor UART.
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| /Zephyr-latest/doc/hardware/cache/ |
| D | guide.rst | 27 When dealing with memory shared between a processor core and other bus masters,
28 cache coherency needs to be considered. Typically processor caches exist as
29 close to each processor core as possible to maximize performance gain. Because
31 processor's cache, resulting in what appears to be corrupt data. If you are
32 moving data using DMA and the processor doesn't see the data you expect, cache
35 There are multiple approaches to ensuring that the data seen by the processor
140 processor has written to it and before a remote bus master reads from that
146 caching in which data writes from the processor core propagate through to
153 be refreshed from main memory when the processor next reads from the specified
160 the processor reads from the buffer.
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| /Zephyr-latest/drivers/ipm/ |
| D | Kconfig | 4 bool "Inter-Processor Mailbox (IPM) drivers"
6 Include interrupt-based inter-processor mailboxes
55 Inter Processor Interrupt driver for AMD-Xilinx
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| D | Kconfig.stm32 | 13 int "STM32 IPCC Processor ID"
18 use to define the Processor ID for IPCC access
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| /Zephyr-latest/drivers/crypto/ |
| D | Kconfig.mcux_dcp | 5 bool "NXP Data Co-Processor (DCP) driver"
12 Enable NXP Data Co-Processor (DCP) driver.
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| /Zephyr-latest/tests/subsys/mgmt/mcumgr/smp_version/ |
| D | testcase.yaml | 11 # FIXME: Exclude systems whereby the processor type is not known and emits a warning
24 # FIXME: Exclude systems whereby the processor type is not known and emits a warning
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| /Zephyr-latest/lib/open-amp/ |
| D | resource_table.h | 26 #define VRING_RX_ADDRESS -1 /* allocated by Master processor */
27 #define VRING_TX_ADDRESS -1 /* allocated by Master processor */
28 #define VRING_BUFF_ADDRESS -1 /* allocated by Master processor */
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| /Zephyr-latest/arch/arm/core/cortex_m/ |
| D | Kconfig | 186 This option signifies the use of an ARMv6-M processor
187 implementation, or the use of an ARMv8-M processor
203 This option signifies the use of an ARMv8-M processor
218 This option signifies the use of an ARMv7-M processor
220 ARMv8-M processor implementation supporting the Main
238 This option signifies the use of an ARMv8-M processor
248 This option signifies the use of an ARMv8.1-M processor
259 This option signifies the use of an ARMv8-M processor
268 This option signifies the use of an ARMv7-M processor
269 implementation, or the use of an ARMv8-M processor
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| /Zephyr-latest/soc/atmel/sam/common/ |
| D | Kconfig | 25 processor clock.
45 The processor clock is (MAINCK * (MULA + 1) / DIVA).
58 The processor clock is (MAINCK * (MULA + 1) / DIVA).
72 This divisor defines a ratio between processor clock (HCLK)
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| /Zephyr-latest/boards/microchip/mec172xevb_assy6906/ |
| D | Kconfig.defconfig | 27 # processor clock divider register. We assume PCR processor clock divider
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