| /Zephyr-latest/scripts/utils/ |
| D | pinctrl_nrf_migrate.py | 4 # SPDX-License-Identifier: Apache-2.0
11 nRF-based boards using the old <signal>-pin properties to select peripheral
13 file by removing old pin-related properties replacing them with pinctrl states.
14 A board-pinctrl.dtsi file will be generated containing the configuration for
28 -i path/to/board.dts
29 [--no-backup]
30 [--skip-nrf-check]
31 [--header ""]
35 .. code-block:: devicetree
41 tx-pin = <5>;
[all …]
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | digilent,pmod.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 This binding provides a nexus mapping for 8 pins where parent pins 0
9 correspond to IO5 through IO8, as depicted below for a 12-pin connector.
11 12-pin Pmod interface:
17 - GND GND -
18 - VDD VDD -
20 This binding can also be used with the 6-pin Pmod connector variant which
21 is a proper subset of the 12-pin connector. In that case parent pins 4
22 through 7 are omitted from the GPIO nexus node, resulting in a mapping
25 6-pin Pmod interface:
[all …]
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| D | nuvoton,npcx-gpio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Nuvoton, NPCX-GPIO node
6 compatible: "nuvoton,npcx-gpio"
8 include: [gpio-controller.yaml, base.yaml]
19 wui-maps:
23 Mapping table between Wake-Up Input (WUI) and 8 IOs belong to this device.
27 For example the WUI mapping on NPCX7 GPIO8 would be
28 wui-maps = <&wui_io80 &wui_io81 &wui_io82 &wui_io83
31 lvol-maps:
34 Mapping table between Low-Voltage controllers and 8 IOs belong to
[all …]
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| D | x-powers,axp192-gpio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 AX192 features 5 native GPIOs. In addition the EXTEN pin can be configured
9 Pin-Mapping is as follows
17 compatible: "x-powers,axp192-gpio"
19 include: gpio-controller.yaml
22 "#gpio-cells":
31 gpio-cells:
32 - pin
33 - flags
|
| D | ambiq,gpio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Ambiq GPIO provides the GPIO pin mapping for GPIO child nodes.
8 It uses 128 continuous 32-bit registers to configure the GPIO pins.
9 This binding provides a pin mapping to solve the limitation of the maximum
13 devicetree and some child nodes which are compatible with "ambiq,gpio-bank"
21 gpio-map-mask = <0xffffffe0 0xffffffc0>;
22 gpio-map-pass-thru = <0x1f 0x3f>;
23 gpio-map = <
30 #gpio-cells = <2>;
31 #address-cells = <1>;
[all …]
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| D | particle-gen3-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 "shields" but use a different orientation and pin numbering scheme.
11 * A 12-pin header on the right. 9 pins on this header are exposed
13 * A 16-pin header. 13 pins on this header are exposed by this
16 This binding provides a nexus mapping for 22 pins where parent pins
17 0 through 8 correspond to the pins on the 12-pin header, starting
19 16-pin header, skipping the bottom pin then assigning 9 through 19,
20 skipping over GND, and replacing the lower 3V3 with pin 20. The
24 - 3V3
26 - GND
[all …]
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| D | sparkfun,micromod-gpio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
12 * An 6-pin Power Supply header. No pins on this header are exposed
17 * 2 i2c buses. Only the corresponding interrupt pin is exposed by
19 * 2 SPI buses not exposed by this binding. Only SPI CS control pin
24 * 12 General purpose pins (G0 - G11).
26 This binding provides a nexus mapping for the analog, digital and
29 - 00 -> A0 PIN 34
30 - 01 -> A1 PIN 38
31 - 02 -> D0 PIN 10
32 - 03 -> D1/CAM_TRIG PIN 18
[all …]
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| D | atmel-xplained-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Xplained layout provide a standard 10 pin header. A board can have
12 every pin can be defined as general purpose GPIO.
29 https://www.microchip.com/development-tools/xplained-boards
30 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Developmen…
32 This binding provides a nexus mapping for 10 pins where pins are disposed
36 Bind Pin Name Pin Pin Pin Name Bind
43 compatible: "atmel-xplained-header"
45 include: [gpio-nexus.yaml, base.yaml]
|
| D | arduino-mkr-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 * One side of the 14-pin header is analog inputs and digital signals.
10 A1 to A6 is Analog input. The outside pin is AREF.
11 A0 that is next to AREF used as a DAC output pin too.
12 D0-D5 is a digital output.
13 * The other side 14-pin header is power supplies and peripheral interface.
14 There are 5V and VCC power supply, GND, and RESET pin. UART, I2C,
17 This binding provides a nexus mapping for 22 pins where parent pins 0
21 - AREF 5V -
22 15 A0/D15/DAC0 VIN -
[all …]
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| D | arduino-header-r3.yaml | 3 # SPDX-License-Identifier: Apache-2.0
11 Proceeding counter-clockwise:
12 * An 8-pin Power Supply header. No pins on this header are exposed
14 * A 6-pin Analog Input header. This has analog input signals
16 * An 8-pin header (opposite Analog Input). This has digital input
18 * A 10-pin header (opposite Power Supply). This has six additional
23 This binding provides a nexus mapping for 20 pins where parent pins 0
29 AREF -
30 GND -
31 - N/C D13 19
[all …]
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| D | adafruit-feather-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 Proceeding counter-clockwise:
10 * A 16-pin header. 12 pins on this header are exposed
12 * A 12-pin header. 9 pins on this header are exposed
15 This binding provides a nexus mapping for 21 pins where parent pins 0
19 - RESET
20 - 3V3
21 - 3V3
22 - GND
23 0 A0 - VBAT
[all …]
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| D | arduino-nano-header-r3.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 * A 15-pin header with mostly digital signals. The additional NRST (pin3)
10 and GND (pin 4) pins are not exposed by this binding.
11 * A 15-pin Analog Input and power supply header. This has analog input
15 This binding provides a nexus mapping for 22 pins where parent pins 0
19 1 D1 VIN -
20 0 D0 GND -
21 - RESET RESET -
22 - GND 5V -
31 10 D10 AREF -
[all …]
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| D | seeed-xiao-header.yaml | 4 # SPDX-License-Identifier: Apache-2.0
12 Proceeding counter-clockwise:
13 * A 7-pin Digital/Analog Input header. This has input signals
15 * An 7-pin header Power and Digital/Analog Input header. This
19 This binding provides a nexus mapping for 10 pins where parent pins 0
22 0 D0 5V -
23 1 D1 GND -
24 2 D2 3V3 -
31 compatible: "seeed,xiao-gpio"
33 include: [gpio-nexus.yaml, base.yaml]
|
| D | m5stack,atom-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Pin-header exposed on M5Stack Atom devices.
7 This binding provides a nexus mapping for 9 pins as depicted below.
15 compatible: "m5stack,atom-header"
17 include: [gpio-nexus.yaml, base.yaml]
|
| /Zephyr-latest/dts/bindings/interrupt-controller/ |
| D | infineon,xmc4xxx-intc.yaml | 3 compatible: "infineon,xmc4xxx-intc"
11 port-line-mapping:
15 An array to store the Event Request Unit (ERU) configuration for a given port/pin
17 XMC4XXX_INTC_SET_LINE_MAP(port, pin, eru_src, line);
18 eru_src defines where the specific port/pin combination is connected in the ERU.
|
| /Zephyr-latest/drivers/gpio/ |
| D | gpio_kscan_ite_it8xxx2.c | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
21 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio output enable register (bit mapping to pin) */
23 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio control register (bit mapping to pin) */
25 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio data register (bit mapping to pin) */
27 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio data mirror register (bit mapping to pin) */
29 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio open drain register (bit mapping to pin) */
39 gpio_pin_t pin, in gpio_kscan_it8xxx2_configure() argument
42 const struct gpio_kscan_cfg *const config = dev->config; in gpio_kscan_it8xxx2_configure()
43 volatile uint8_t *reg_ksi_kso_gctrl = config->reg_ksi_kso_gctrl; in gpio_kscan_it8xxx2_configure()
[all …]
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| /Zephyr-latest/dts/bindings/i2c/ |
| D | microchip,xec-i2c.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-i2c"
8 include: [i2c-controller.yaml, pinctrl-device.yaml]
16 description: soc block mapping to pin
24 girq-bit:
34 pinctrl-0:
37 pinctrl-names:
40 sda-gpios:
41 type: phandle-array
44 The SDA pin for the selected port. Pin choice for port is
[all …]
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | ambiq,apollo3-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 The Ambiq Apollo3 pin controller is a node responsible for controlling
6 pin function selection and pin properties, such as routing a UART0 TX
7 to pin 60 and enabling the pullup resistor on that pin.
16 All device pin configurations should be placed in child nodes of the
19 /* You can put this in places like a board-pinctrl.dtsi file in
23 /* include pre-defined combinations for the SoC variant used by the board */
24 #include <dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h>
33 input-enable;
38 The 'uart0_default' child node encodes the pin configurations for a
[all …]
|
| /Zephyr-latest/arch/xtensa/core/ |
| D | README_MMU.txt | 14 4-way-set-associative bank of entries mapping 4k pages, and 3-6
16 for mapping pages larger than 4k, which Zephyr does not directly
22 architecture technically supports separately-virtualized instruction
33 Live TLB entries are tagged with an 8-bit "ASID" value derived from
36 non-kernel address space will get a separate ring 3 ASID set in RASID,
44 ## Virtually-mapped Page Tables
59 memory fetch vs. e.g. the 2-5 fetches required to walk a page table on
68 1048576 4-byte PTE entries, each describing a mapping for 4k of
76 entries mapping all of them. If we are missing a TLB entry for the
87 the exception handler may result in an invalid/inapplicable mapping
[all …]
|
| /Zephyr-latest/doc/hardware/pinctrl/ |
| D | index.rst | 1 .. _pinctrl-guide:
3 Pin Control
6 This is a high-level guide to pin control. See :ref:`pinctrl_api` for API
12 The hardware blocks that control pin multiplexing and pin configuration
13 parameters such as pin direction, pull-up/down resistors, etc. are named **pin
14 controllers**. The pin controller's main users are SoC hardware peripherals,
16 map ``I2C0`` ``SDA`` signal to pin ``PX0``. Not only that, but it usually allows
17 configuring certain pin settings that are necessary for the correct functioning
18 of a peripheral, for example, the slew-rate depending on the operating
20 range from simple pull-up/down options to more advanced settings such as
[all …]
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| /Zephyr-latest/dts/bindings/display/ |
| D | solomon,ssd1306fb-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 include: display-controller.yaml
7 segment-offset:
10 description: 8-bit column start address for Page Addressing Mode
12 page-offset:
17 display-offset:
20 description: mapping of the display start line to one of COM0 .. COM63
22 multiplex-ratio:
27 segment-remap:
31 com-invdir:
[all …]
|
| /Zephyr-latest/dts/bindings/input/ |
| D | ite,it8801-kbd.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: ITE IT8801 I2C-based keyboard matrix scan controller
6 compatible: "ite,it8801-kbd"
8 include: [kbd-matrix-common.yaml, pinctrl-device.yaml]
17 Switching the pin to KSO alternate function.
19 kso-mapping:
22 row-size:
25 col-size:
|
| /Zephyr-latest/dts/bindings/mfd/ |
| D | ite,it8801-mfd.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 ITE IT8801 ioexpander multi-function device drivers.
8 An example configuration using the it8801-common-cfg.dtsi template:
12 compatible = "ite,it8801-mfd";
14 * SMBus address (7-bit without R/W)
15 * SMB_ADDR pin is 0, SMBus address is 0x38
16 * SMB_ADDR pin is 1, SMBus address is 0x39
19 irq-gpios = <&gpioa 1 0>; /* SMB_INT# */
22 #include <ite/it8801-common-cfg.dtsi>
24 /* sub-devices available at nodelabels:
[all …]
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| /Zephyr-latest/drivers/led_strip/ |
| D | ws2812_gpio.c | 6 * SPDX-License-Identifier: Apache-2.0
25 #include <zephyr/dt-bindings/led/led.h>
42 * https://github.com/zephyrproject-rtos/zephyr/issues/11917.
47 * Per Arm docs, both Rd and Rn must be r0-r7, so we use the "l"
57 #define ONE_BIT(base, pin) do { \ argument
64 [p] "l" (pin)); } while (false)
67 #define ZERO_BIT(base, pin) do { \ argument
74 [p] "l" (pin)); } while (false)
78 const struct ws2812_gpio_cfg *config = dev->config; in send_buf()
79 volatile uint32_t *base = (uint32_t *)&NRF_GPIO->OUTSET; in send_buf()
[all …]
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| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_ti_cc32xx.c | 3 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/pinctrl/ti-cc32xx-pinctrl.h>
15 /* pin to pad mapping (255 indicates invalid pin) */
26 uint8_t pin; in pinctrl_configure_pin() local
28 pin = (pincfg >> TI_CC32XX_PIN_POS) & TI_CC32XX_PIN_MSK; in pinctrl_configure_pin()
29 if ((pin >= ARRAY_SIZE(pin2pad)) || (pin2pad[pin] == 255U)) { in pinctrl_configure_pin()
30 return -EINVAL; in pinctrl_configure_pin()
33 sys_write32(pincfg & MEM_GPIO_PAD_CONFIG_MSK, DT_INST_REG_ADDR(0) + (pin2pad[pin] << 2U)); in pinctrl_configure_pin()
|
