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/Zephyr-latest/dts/bindings/clock/
Dst,stm32f105-pll2-clock.yaml7 Takes clk_hse as input clock, using prediv as prescaler.
11 f(PLL2CLK) = f(PLL2IN) / PREDIV * PLLMUL --> PLL (System Clock)
Dst,stm32f0-pll-clock.yaml18 f(PLLIN) = f(input_clk) / PREDIV
23 f(PLLIN) = f(input_clk) / PREDIV
Dst,stm32f105-pll-clock.yaml17 f(PLLIN) = f(input_clk) / PREDIV if input_clk = clk_hse or pll2
48 prediv:
Dst,stm32f100-pll-clock.yaml18 f(PLLIN) = f(input_clk) / PREDIV if input_clk = clk_hse
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Df0_i2c1_hsi.overlay32 /delete-property/ prediv;
54 prediv = <2>;
Df3_i2c1_hsi.overlay32 /delete-property/ prediv;
54 prediv = <2>;
Df4_i2s2_pll.overlay32 /delete-property/ prediv;
/Zephyr-latest/boards/st/nucleo_f030r8/
Dnucleo_f030r8_stm32f030x8_1.overlay16 prediv = <2>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/
Df0_f3_pll_32_hsi_8.overlay18 prediv = <2>;
Df0_f3_pll_32_hse_8.overlay19 prediv = <4>;
Dclear_f0_f1_f3_clocks.overlay33 /delete-property/ prediv;
/Zephyr-latest/soc/nxp/imx/imx8m/m7/
Dsoc.c58 /* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
63 .preDiv = 3U,
71 .preDiv = 3U,
79 .preDiv = 3U,
/Zephyr-latest/boards/seagate/legend/
Dlegend_stm32f070xb_25ssd.overlay19 prediv = <1>;
Dlegend_stm32f070xb_25hdd.overlay32 prediv = <1>;
Dlegend_stm32f070xb_35.overlay33 prediv = <1>;
/Zephyr-latest/drivers/clock_control/
Dclock_stm32f0_f3.c39 * PLL PREDIV in config_pll_sysclock()
99 * PLL PREDIV in get_pllout_frequency()
Dclock_stm32f1.c66 /* In case PLL source is not HSI, set prediv case by case */ in config_pll_sysclock()
68 /* PLL prediv */ in config_pll_sysclock()
/Zephyr-latest/boards/others/stm32f030_demo/
Dstm32f030_demo.dts42 prediv = <1>;
/Zephyr-latest/boards/st/stm3210c_eval/
Dstm3210c_eval.dts55 prediv = <1>;
/Zephyr-latest/boards/st/stm32373c_eval/
Dstm32373c_eval.dts57 prediv = <1>;
/Zephyr-latest/boards/fysetc/ucan/
Ducan.dts54 prediv = <1>;
/Zephyr-latest/boards/others/candlelight/
Dcandlelight.dts54 prediv = <1>;
/Zephyr-latest/soc/nxp/imx/imx8m/m4_mini/
Dsoc.c61 .preDiv = 5U,
70 .preDiv = 5U,
/Zephyr-latest/boards/st/nucleo_f031k6/
Dnucleo_f031k6.dts54 prediv = <4>;
/Zephyr-latest/boards/st/nucleo_f042k6/
Dnucleo_f042k6.dts54 prediv = <1>;

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