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/Zephyr-Core-3.6.0/dts/bindings/clock/
Dst,stm32wb-pll-clock.yaml18 f(PLL_Q) = f(VCO clock) / PLLQ --> PLLQCLK
61 Main PLL division factor for PLLQCLK
/Zephyr-Core-3.6.0/drivers/clock_control/
Dclock_stm32_ll_mco.h39 #error "PLLQCLK is not a valid clock source on your SOC"