Home
last modified time | relevance | path

Searched full:origin (Results 1 – 25 of 113) sorted by relevance

12345

/Zephyr-latest/soc/gaisler/gr716a/
Dlinker.ld22 bootprom (rx) : ORIGIN = 0x00000000, LENGTH = 4K symbol
23 extprom (rx) : ORIGIN = 0x01000000, LENGTH = 16M
24 spi0 (rx) : ORIGIN = 0x02000000, LENGTH = 32M
25 spi1 (rx) : ORIGIN = 0x04000000, LENGTH = 32M
26 RAM (rw) : ORIGIN = 0x30000000, LENGTH = 64K
27 SRAM (x) : ORIGIN = 0x31000000, LENGTH = 128K
28 extram (rwx) : ORIGIN = 0x40000000, LENGTH = 256M
30 IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
/Zephyr-latest/samples/modules/tflite-micro/magic_wand/renode/
Dlitex-vexriscv-tflite.resc9 machine LoadPlatformDescription $ORIGIN/litex-vexriscv-tflite.repl
18 i2c.adxl345 FeedSample $ORIGIN/circle.data
21 i2c.adxl345 FeedSample $ORIGIN/angle.data
24 i2c.adxl345 FeedSample $ORIGIN/circle.data
27 i2c.adxl345 FeedSample $ORIGIN/angle.data
/Zephyr-latest/soc/gaisler/leon3/
Dlinker.ld18 rom (rx) : ORIGIN = 0x00000000, LENGTH = 512M symbol
19 RAM (rwx) : ORIGIN = CONFIG_SRAM_BASE_ADDRESS, LENGTH = KB(CONFIG_SRAM_SIZE)
21 IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
/Zephyr-latest/soc/nxp/imx/imx8m/m7/
Dlinker.ld13 DDR (wx) : ORIGIN = 0x80400000, LENGTH = 0x00C00000 symbol
15 DDR (wx) : ORIGIN = 0x80000000, LENGTH = 0x01000000
/Zephyr-latest/soc/silabs/silabs_siwx91x/siwg917/
Dlinker.ld10 udma0 (rwx) : ORIGIN = 0x0002fc00, LENGTH = 0x00000400 symbol
11 udma1 (rwx) : ORIGIN = 0x24061c00, LENGTH = 0x00000400
/Zephyr-latest/include/zephyr/arch/x86/
Dmemory.ld89 ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = FLASH_ROM_SIZE symbol
91 ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = PHYS_RAM_AVAIL
97 RAM (wx) : ORIGIN = KERNEL_BASE_ADDR, LENGTH = KERNEL_RAM_SIZE
102 LOCORE (wx) : ORIGIN = LOCORE_BASE, LENGTH = LOCORE_SIZE
113 IDT_LIST : ORIGIN = 0xFFFF1000, LENGTH = 2K
/Zephyr-latest/soc/nxp/imxrt/imxrt118x/
Dlinker.ld16 …SDRAM (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram0… symbol
20 …hyperram0 (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(hyperram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL…
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dlinker.ld18 …FLEXSPI1 (wx) : ORIGIN = DT_REG_ADDR_BY_IDX(DT_NODELABEL(flexspi1), 1), LENGTH = DT_REG_SIZE_BY_I… symbol
21 …FLEXSPI2 (wx) : ORIGIN = DT_REG_ADDR_BY_IDX(DT_NODELABEL(flexspi2), 1), LENGTH = DT_REG_SIZE_BY_I…
/Zephyr-latest/tests/lib/devicetree/memory_region_flags/pytest/
Dtest_memory_region_flags.py43 origin = node.props["reg"].val[0]
47 r"\s*:\s*ORIGIN\s*=\s*\(?([0-9A-Fa-fx]*)\)?,\s*LENGTH\s*=\s*\(?([0-9A-Fa-fx]*)\)?"
57 if m and smart_int(m[1]) == origin and smart_int(m[2]) == length:
/Zephyr-latest/include/zephyr/arch/nios2/
Dlinker.ld61 RESET (rx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20 symbol
62 FLASH (rx) : ORIGIN = _RESET_VECTOR + 0x20 , LENGTH = (_ROM_SIZE - 0x20 - ROM_END_OFFSET)
63 RAM (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)
65 IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
73 RESET (wx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20
74 RAM (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)
77 IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
/Zephyr-latest/soc/sensry/ganymed/sy1xx/common/
Dlinker.ld41 L2_START (rx) : ORIGIN = 0x1c010000, LENGTH = 0x00000080 symbol
42 L2_VALIDITY (rx) : ORIGIN = 0x1c010080, LENGTH = 0x00000080
44 ROM (rx) : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE /* 392kb */
45 RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE /* 2097kb */
47 L2_PRIV_CH0 : ORIGIN = 0x1c004100, LENGTH = 0x2000 /* uDMA access */
53 IDT_LIST : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
/Zephyr-latest/doc/
DLICENSING.rst16 * *Origin:* Linux Kernel
28 * *Origin:* Coccinelle
50 * *Origin:* GCC, the GNU Compiler Collection
71 * *Origin:* ThreadX
92 * *Origin:* OpenThread
/Zephyr-latest/include/zephyr/arch/arc/v2/
Dlinker.ld59 FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_SIZE symbol
62 ICCM (rwx) : ORIGIN = ICCM_START, LENGTH = ICCM_SIZE
65 SRAM (rwx) : ORIGIN = SRAM_START, LENGTH = SRAM_SIZE
68 DCCM (rw) : ORIGIN = DCCM_START, LENGTH = DCCM_SIZE
71 XCCM (rw) : ORIGIN = XCCM_START, LENGTH = XCCM_SIZE
74 YCCM (rw) : ORIGIN = YCCM_START, LENGTH = YCCM_SIZE
77 IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
/Zephyr-latest/.github/workflows/
Dcoding_guidelines.yml44 git rebase origin/${BASE_REF}
50 ./scripts/ci/guideline_check.py --output output.txt -c origin/${BASE_REF}..
Dcompliance.yml34 [[ "$(git rev-list --merges --count origin/${BASE_REF}..)" == "0" ]] || \
38 git rebase origin/${BASE_REF}
86 -c origin/${BASE_REF}..
/Zephyr-latest/soc/aspeed/ast10x0/
Dlinker.ld8 SRAM_NC (wx) : ORIGIN = CONFIG_SRAM_NC_BASE_ADDRESS, LENGTH = CONFIG_SRAM_NC_SIZE * 1024 symbol
/Zephyr-latest/boards/renode/riscv32_virtual/support/
Driscv32_virtual.resc8 machine LoadPlatformDescription $ORIGIN/riscv32_virtual.repl
/Zephyr-latest/soc/nxp/s32/s32k3/
Dlinker.ld10 IVT_HEADER (r) : ORIGIN = CONFIG_FLASH_BASE_ADDRESS + CONFIG_IVT_HEADER_OFFSET, symbol
/Zephyr-latest/boards/antmicro/myra_sip_baseboard/support/
Dmyra_sip_baseboard.resc8 machine LoadPlatformDescription $ORIGIN/myra_sip_baseboard.repl
/Zephyr-latest/boards/microchip/m2gl025_miv/support/
Dm2gl025_miv.resc8 machine LoadPlatformDescription $ORIGIN/m2gl025_miv.repl
/Zephyr-latest/boards/renode/cortex_r8_virtual/support/
Dcortex_r8_virtual.resc8 machine LoadPlatformDescription $ORIGIN/cortex_r8_virtual.repl
/Zephyr-latest/samples/boards/intel/adsp/code_relocation/
Dlinker_xtensa_intel_adsp_cavs.ld44 SRAM2 (wx) : ORIGIN = (SRAM2_ADDR), LENGTH = RAM_SIZE2 symbol
45 SRAM3 (wx) : ORIGIN = (SRAM3_ADDR), LENGTH = RAM_SIZE3
46 SRAM4 (wx) : ORIGIN = (SRAM4_ADDR), LENGTH = RAM_SIZE4
/Zephyr-latest/include/zephyr/math/
Dinterpolation.h56 /* Shift input to origin */ in linear_interpolate()
67 /* Apply slope, undo origin shift and round */ in linear_interpolate()
/Zephyr-latest/doc/contribute/
Dguidelines.rst121 Developer Certification of Origin (DCO)
125 project requires the Developer Certificate of Origin (DCO) process to be
139 Developer's Certificate of Origin 1.1
675 <https://github.com/zephyrproject-rtos/zephyr>`_ from ``origin`` to
678 git remote rename origin upstream
680 Let Git know about the fork you just created, naming it ``origin``::
682 git remote add origin https://github.com/<your github id>/zephyr
690 origin https://github.com/<your github id>/zephyr (fetch)
691 origin https://github.com/<your github id>/zephyr (push)
704 git checkout -b fix_out_of_date_patch origin/net
[all …]
/Zephyr-latest/soc/nxp/imxrt/imxrt10xx/
Dlinker.ld16 …SDRAM (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram0… symbol

12345