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| /Zephyr-Core-3.5.0/include/zephyr/app_memory/ |
| D | mem_domain.h | 3 * Copyright (c) 2018-2020 Intel Corporation
5 * SPDX-License-Identifier: Apache-2.0
22 * @defgroup mem_domain_apis Memory domain APIs
31 * @brief Statically declare a memory partition
45 * @brief Memory Partition
47 * A memory partition is a region of memory in the linear address space
52 * underlying memory management hardware; arbitrary values are unlikely
53 * to work.
56 /** start address of memory partition */
58 /** size of memory partition */
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| /Zephyr-Core-3.5.0/include/zephyr/sys/ |
| D | mem_blocks.h | 4 * SPDX-License-Identifier: Apache-2.0
10 * @brief Memory Blocks Allocator
31 * @defgroup mem_blocks_apis Memory Blocks APIs
37 * @brief Memory Blocks Allocator
42 * @brief Multi Memory Blocks Allocator
49 * @brief Memory Blocks Allocator
56 * @brief Multi Memory Blocks Allocator
61 * @brief Multi memory blocks allocator choice function
63 * This is a user-provided functions whose responsibility is selecting
64 * a specific memory blocks allocator based on the opaque cfg value,
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| D | sys_io.h | 1 /* Port and memory mapped registers I/O operations */
6 * SPDX-License-Identifier: Apache-2.0
27 * @brief Output a byte to an I/O port
29 * This function writes a byte to the given port.
31 * @param data the byte to write
32 * @param port the port address where to write the byte
41 * @param port the port address from where to read the byte
48 * @brief Output a 16 bits to an I/O port
50 * This function writes a 16 bits to the given port.
52 * @param data the 16 bits to write
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| D | sys_heap.h | 4 * SPDX-License-Identifier: Apache-2.0
21 * power-of-two buckets.
25 * bytes for heaps >256kb or on 64 bit systems), plus a log2-sized
26 * array of 2-word bucket headers. No coarse alignment restrictions
30 * Simple API. Initialize at runtime with any blob of memory and not
31 * a macro-generated, carefully aligned static array. Allocate and
37 * to the smallest block guaranteed to fit. Split memory remaining in
38 * the chunk is always returned immediately to the heap for other
43 * that has a compile-time-configurable upper bound, setting this to
45 * list), objectively fast (~hundred instructions) and and amenable to
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/mm/ |
| D | mm_drv_bank.h | 4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Memory Banks Driver APIs
11 * This contains generic APIs to be used by a system-wide memory management
12 * driver to track page usage within memory banks. It is incumbent upon the
13 * caller to ensure that proper locking is used to protect the data when
33 * @brief Initialize a memory bank's data structure
35 * The driver may wish to track various information about the memory banks
37 * that information. Since at the power on all memory banks are switched on
41 * @param bank Pointer to the memory bank structure used for tracking
42 * @param bank_pages Number of pages in the memory bank
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| D | system_mm.h | 4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Memory Management Driver APIs
11 * This contains APIs for a system-wide memory management
27 * @brief Memory Management Driver APIs
28 * @defgroup mm_drv_apis Memory Management Driver APIs
40 /** Write-through caching */
43 /** Full write-back caching */
47 #define SYS_MM_MEM_CACHE_MASK (BIT(3) - 1)
51 * Default should be read-only, no user, no exec.
54 /** Region will have read/write access (and not read-only) */
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| /Zephyr-Core-3.5.0/doc/kernel/usermode/ |
| D | memory_domain.rst | 3 Memory Protection Design
6 Zephyr's memory protection design is geared towards microcontrollers with MPU
7 (Memory Protection Unit) hardware. We do support some architectures, such as x86,
8 which have a paged MMU (Memory Management Unit), but in that case the MMU is
12 can be considered to have an MPU with an unlimited number of programmable
15 There are a few different levels on how memory access is configured when
16 Zephyr memory protection features are enabled, which we will describe here:
18 Boot Time Memory Configuration
24 - Any configuration of memory regions which need to have special caching or
25 write-back policies for basic hardware and driver function. Note that most
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| /Zephyr-Core-3.5.0/doc/kernel/memory_management/ |
| D | slabs.rst | 3 Memory Slabs
6 A :dfn:`memory slab` is a kernel object that allows memory blocks
7 to be dynamically allocated from a designated memory region.
8 All memory blocks in a memory slab have a single fixed size,
9 allowing them to be allocated and released efficiently
10 and avoiding memory fragmentation concerns.
19 Any number of memory slabs can be defined (limited only by available RAM). Each
20 memory slab is referenced by its memory address.
22 A memory slab has the following key properties:
30 * A **buffer** that provides the memory for the memory slab's blocks.
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| D | sys_mem_blocks.rst | 3 Memory Blocks Allocator
6 The Memory Blocks Allocator allows memory blocks to be dynamically
7 allocated from a designated memory region, where:
9 * All memory blocks have a single fixed size.
14 This is useful for operations such as scatter-gather DMA transfers.
17 buffer (unlike memory slab). This allows the buffer to reside in
18 memory regions where these can be powered down to conserve energy.
27 Any number of Memory Blocks Allocator can be defined (limited only by
28 available RAM). Each allocator is referenced by its memory address.
30 A memory blocks allocator has the following key properties:
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| D | heap.rst | 3 Memory Heaps
6 Zephyr provides a collection of utilities that allow threads to
7 dynamically allocate memory.
15 The simplest way to define a heap is statically, with the
17 with a given name that manages a memory region of the
20 Heaps can also be created to manage arbitrary regions of
21 application-controlled memory using :c:func:`k_heap_init`.
23 Allocating Memory
26 Memory can be allocated from a heap using :c:func:`k_heap_alloc`,
28 desired. This functions similarly to standard C ``malloc()``,
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| D | shared_multi_heap.rst | 6 The shared multi-heap memory pool manager uses the multi-heap allocator to
7 manage a set of reserved memory regions with different capabilities /
8 attributes (cacheable, non-cacheable, etc...).
10 All the different regions can be added at run-time to the shared multi-heap
12 be used by drivers or applications to request memory with certain capabilities.
16 1. At boot time some platform code initialize the shared multi-heap framework
17 using :c:func:`shared_multi_heap_pool_init()` and add the memory regions to
21 2. Each memory region encoded in a :c:type:`shared_multi_heap_region`
22 structure. This structure is also carrying an opaque and user-defined
23 integer value that is used to define the region capabilities (for example:
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/misc/ft8xx/ |
| D | ft8xx_common.h | 4 * SPDX-License-Identifier: Apache-2.0
22 * @brief FT8xx functions to write and read memory
29 * @brief Write 1 byte (8 bits) to FT8xx memory
31 * @param address Memory address to write to
32 * @param data Byte to write
37 * @brief Write 2 bytes (16 bits) to FT8xx memory
39 * @param address Memory address to write to
40 * @param data Value to write
45 * @brief Write 4 bytes (32 bits) to FT8xx memory
47 * @param address Memory address to write to
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| /Zephyr-Core-3.5.0/doc/services/mem_mgmt/ |
| D | index.rst | 3 Memory Attributes
6 It is possible in the devicetree to mark the memory regions with attributes by
7 using the ``zephyr,memory-attr`` property. This property and the related memory
8 region can then be retrieved at run-time by leveraging a provided helper
12 and explained in :zephyr_file:`include/zephyr/dt-bindings/memory-attr/memory-attr.h`.
14 For example, to mark a memory region in the devicetree as non-volatile, cacheable,
15 out-of-order:
17 .. code-block:: devicetree
19 mem: memory@10000000 {
20 compatible = "mmio-sram";
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| /Zephyr-Core-3.5.0/include/zephyr/multi_heap/ |
| D | shared_multi_heap.h | 4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public API for Shared Multi-Heap framework
28 * @brief Shared Multi-Heap (SMH) interface
29 * @defgroup shared_multi_heap Shared multi-heap interface
33 * The shared multi-heap manager uses the multi-heap allocator to manage a set
34 * of memory regions with different capabilities / attributes (cacheable,
35 * non-cacheable, etc...).
37 * All the different regions can be added at run-time to the shared multi-heap
39 * can be used by drivers or applications to request memory with certain
44 * - At boot time some platform code initialize the shared multi-heap
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| /Zephyr-Core-3.5.0/lib/os/ |
| D | Kconfig.heap | 3 # SPDX-License-Identifier: Apache-2.0
5 menu "Heap and Memory Allocation"
13 environments that require sensitive detection of memory
22 requested allocation) to maintain constant time performance.
23 Setting this to a high level will cause the heap to return
41 This allows application to listen for sys_heap events,
42 such as memory allocation and de-allocation.
47 Hidden option to enable API for registering and notifying
48 listeners of certain events related to a heap usage,
57 Heaps using reduced-size chunk headers can accommodate so called
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| /Zephyr-Core-3.5.0/arch/arm/core/mpu/ |
| D | arm_core_mpu_dev.h | 4 * SPDX-License-Identifier: Apache-2.0
22 * @brief Maximum number of memory domain partitions
24 * This internal macro returns the maximum number of memory partitions, which
25 * may be defined in a memory domain, given the amount of available HW MPU
34 * on top of the statically configured memory regions, the maximum number of
35 * memory domain partitions is set to half of the number of available MPU
36 * regions. This ensures that in the worst-case where there are gaps between
37 * the memory partitions of the domain, the desired memory map can still be
45 * on top of the statically configured memory regions, the maximum number
46 * of memory domain partitions is equal to the number of available MPU regions.
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| D | Kconfig | 1 # Memory Protection Unit (MPU) configuration options
4 # SPDX-License-Identifier: Apache-2.0
18 MCU implements Memory Protection Unit.
21 The ARMv6-M and ARMv7-M MPU architecture requires a power-of-two
24 The NXP MPU as well as the ARMv8-M MPU do not require MPU regions
25 to have power-of-two alignment for base address and region size.
27 The ARMv8-M MPU requires the active MPU regions be non-overlapping.
28 As a result of this, the ARMv8-M MPU needs to fully partition the
29 memory map when programming dynamic memory regions (e.g. PRIV stack
30 guard, user thread stack, and application memory domains), if the
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| /Zephyr-Core-3.5.0/include/zephyr/mem_mgmt/ |
| D | mem_attr.h | 4 * SPDX-License-Identifier: Apache-2.0
11 * @brief Memory-Attr Interface
12 * @defgroup memory_attr_interface Memory-Attr Interface
19 #include <zephyr/dt-bindings/memory-attr/memory-attr.h>
38 * `zephyr,memory-attr`
41 * with the `zephyr,memory-attr` property. The macro is expanded once for each
45 * @param fn macro to invoke
51 * @brief memory-attr region structure.
53 * This structure represents the data gathered from DT about a memory-region
54 * marked with memory attributes.
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| /Zephyr-Core-3.5.0/include/zephyr/debug/ |
| D | gdbstub.h | 4 * SPDX-License-Identifier: Apache-2.0
10 /* Map from CPU exceptions to GDB */
18 /* Access permissions for memory regions */
29 /** Describe one memory region */
31 /** Start address of a memory region */
34 /** End address of a memory region */
37 /** Memory region attributes */
45 * Memory region descriptions used for GDB memory access.
47 * This array specifies which region of memory GDB can access
48 * with read/write attributes. This is used to restrict
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| /Zephyr-Core-3.5.0/dts/bindings/memory-controllers/ |
| D | st,stm32-fmc-sdram.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Flexible Memory Controller (SDRAM controller).
7 The FMC SDRAM controller can be used to interface with external SDRAM
8 memories. Up to 2 SDRAM banks are supported with independent configuration. It
9 is worth to note that while settings are independent, some are shared or are
10 required to be set according to the most constraining device. Refer to the
20 pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4...>;
25 power-up-delay = <100>;
26 num-auto-refresh = <8>;
27 mode-register = <0x220>;
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| /Zephyr-Core-3.5.0/arch/arm64/core/cortex_r/ |
| D | Kconfig | 1 # Memory Protection Unit (MPU) configuration options
6 # SPDX-License-Identifier: Apache-2.0
18 MPU implements Memory Protection Unit.
21 The ARMv8-R MPU architecture requires a power-of-two alignment
24 The ARMv8-R MPU requires the active MPU regions be non-overlapping.
25 As a result of this, the ARMv8-R MPU needs to fully partition the
26 memory map when programming dynamic memory regions (e.g. PRIV stack
27 guard, user thread stack, and application memory domains), if the
29 of the ARMv8-R background memory map. The application developer may
30 enforce full PRIV (kernel) memory partition by enabling the
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| /Zephyr-Core-3.5.0/tests/kernel/mem_slab/mslab/src/ |
| D | main.c | 2 * Copyright (c) 2012-2014 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
8 * @brief Test memory slab APIs
10 * @defgroup kernel_memory_slab_tests Memory Slab Tests
14 * This module tests the following memory slab routines:
21 * One should ensure that the block is released to the same memory slab from
34 /* Number of memory blocks. The minimum number of blocks needed to run the
53 * This routine gets all blocks from the memory slab. It uses semaphores
54 * SEM_REGRESDONE and SEM_HELPERDONE to synchronize between different parts
61 void *ptr[NUMBLOCKS]; /* Pointer to memory block */ in helper_thread()
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| /Zephyr-Core-3.5.0/kernel/ |
| D | Kconfig.vm | 3 # SPDX-License-Identifier: Apache-2.0
5 menu "Virtual Memory Support"
10 Hidden option to enable virtual memory Kconfigs.
23 address from DTS, in which case RAM will be identity-mapped. Some
24 architectures may require RAM to be mapped in this way; they may have
28 this for non-pinned page frames).
30 Otherwise, if RAM isn't identity-mapped:
31 1. It is the architecture's responsibility to transition the
32 instruction pointer to virtual addresses at early boot before
36 regions if RAM is not identity-mapped, or the virtual and physical
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/ |
| D | retained_mem.h | 4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public API for retained memory drivers
31 * @brief Retained memory driver interface
32 * @defgroup retained_mem_interface Retained memory driver interface
39 * @brief Callback API to get size of retained memory area.
46 * @brief Callback API to read from retained memory area.
54 * @brief Callback API to write to retained memory area.
62 * @brief Callback API to clear retained memory area (reset all data to 0x00).
68 * @brief Retained memory driver API
69 * API which can be used by a device to store data in a retained memory area. Retained memory is
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/pcie/ |
| D | controller.h | 10 * SPDX-License-Identifier: Apache-2.0
34 * @brief Function called to read a 32-bit word from an endpoint's configuration space.
36 * Read a 32-bit word from an endpoint's configuration space with the PCI Express Controller
37 * configuration space access method (I/O port, memory mapped or custom method)
48 * @brief Function called to write a 32-bit word to an endpoint's configuration space.
50 * Write a 32-bit word to an endpoint's configuration space with the PCI Express Controller
51 * configuration space access method (I/O port, memory mapped or custom method)
56 * @param data the value to write
62 * @brief Function called to allocate a memory region subset for an endpoint Base Address Register.
64 * When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones
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