Searched full:mio (Results 1 – 13 of 13) sorted by relevance
7 Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller node.11 which can be mapped in the system design tools (MIO pins), or SoC-19 * Bank 0: MIO pins [31:00]20 * Bank 1: MIO pins [53:32] (total: 54 MIO pins)25 * Bank 0: MIO pins [25:00]26 * Bank 1: MIO pins [51:26]27 * Bank 2: MIO pins [77:52] (total: 78 MIO pins, 26 per bank)
7 Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller bank node.10 a bank of the MIO/EMIO GPIO controller integrated in the Processor
2 # Xilinx Processor System MIO / EMIO GPIO controller driver10 bool "Xilinx Processor System MIO / EMIO GPIO controller driver"15 Enable the Xilinx Processor System MIO / EMIO GPIO controller driver.
2 * Xilinx Processor System MIO / EMIO GPIO controller driver47 * This struct contains all data of a PS MIO / EMIO GPIO bank61 * This struct contains all data of a PS MIO / EMIO GPIO bank
2 * Xilinx Processor System MIO / EMIO GPIO controller driver37 * status and data acquisition of each MIO / EMIO GPIO pin associated with74 * IRQ. The ISR iterates all associated MIO / EMIO GPIO pink bank167 * Register & initialize all instances of the Processor System's MIO / EMIO GPIO
2 * Xilinx Processor System MIO / EMIO GPIO controller driver
2 * Xilinx Processor System MIO / EMIO GPIO controller driver30 * Configures an individual pin within a MIO / EMIO GPIO pin bank.420 * @brief Initialize a MIO / EMIO GPIO bank sub-device422 * Initialize a MIO / EMIO GPIO bank sub-device, which is a child451 /* MIO / EMIO bank device definition macros */466 /* Register & initialize all MIO / EMIO GPIO banks specified in the device tree. */
5 bool "Xilinx Zynq 7000 processor system MIO pin controller driver"10 Enable the Xilinx Zynq 7000 processor system MIO pin controller driver.
9 Enable the Xilinx ZynqMP processor system MIO pin controller driver.
24 * [7 ... 0] MIO register number
52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */107 /* MIO pin numbers */163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
17 * For functions that can be selected for a subset of MIO pins,
504 * Added Xilinx PS MIO/EMIO GPIO controller driver.
