Searched full:m0 (Results 1 – 25 of 213) sorted by relevance
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| /Zephyr-latest/dts/bindings/interrupt-controller/ |
| D | cypress,psoc6-intmux.yaml | 8 The PSOC 6 Cortex-M0+ NVIC can handle up to 32 interrupts. This means that
10 to be processed in the Cortex-M0+ CPU.
13 configure the 32 NVIC lines for Cortex-M0+ CPU. Each register handles up to
17 Cortex-M0+ NVIC controller. Note that Cortex-M4 have all interrupt sources
21 configuration and how the Cortex-M0+ NVIC sources are organized. Each
22 channel chX represents a Cortex-M0+ NVIC line and it stores a vector number.
24 Cortex-M0+ NVIC controller line.
31 In practical terms, the Cortex-M0+ requires user to define all NVIC interrupt
33 the Cortex-M0+ Interrupt Multiplexer and interrupts can be processed.
39 Cortex-M0+ NVIC:
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| /Zephyr-latest/soc/infineon/cat1a/ |
| D | Kconfig | 35 Cortex-M0 CPU should boot Cortex-M4
38 ## PSOC™ 6 Cortex M0+ prebuilt images
40 prompt "PSOC™ 6 Cortex M0+ prebuilt images"
42 Choose the prebuilt application image to be executed on the Cortex-M0+ core of the PSOC™ 6
48 DeepSleep prebuilt application image is executed on the Cortex-M0+ core of the PSOC™ 6 BLE
50 application. The Cortex-M0+ application code is placed to internal flash by the Cortex-M4
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| /Zephyr-latest/dts/bindings/cpu/ |
| D | arm,cortex-m0.yaml | 4 description: ARM Cortex-M0 CPU
6 compatible: "arm,cortex-m0"
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| D | arm,cortex-m0+.yaml | 4 description: ARM Cortex-M0+ CPU
6 compatible: "arm,cortex-m0+"
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| /Zephyr-latest/boards/adafruit/feather_m0_lora/doc/ |
| D | index.rst | 6 The Adafruit Feather M0 Lora is a thin, light ARM development
14 - ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz
62 The `Adafruit Feather M0 with LoRa radio module Learn site`_ has detailed
74 The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0
81 The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0
87 The SAMD21 MCU has 6 SERCOM based SPIs. On the Adafruit Feather M0
101 The Semtech SX127x radio chip on the Adafruit Feather M0 with LoRa
108 The Adafruit Feather M0 with LoRa ships with a BOSSA compatible
123 #. Connect the Adafruit Feather M0 with LoRa to your host computer
162 .. _Adafruit Feather M0 with LoRa radio module Learn site:
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| /Zephyr-latest/boards/adafruit/feather_m0_basic_proto/doc/ |
| D | index.rst | 6 The Adafruit Feather M0 Basic Proto is a thin, light ARM development
14 - ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz
59 The `Adafruit Feather M0 Basic Proto Learn site`_ has detailed
71 The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0
78 The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0
84 The SAMD21 MCU has 6 SERCOM based SPIs. On the Adafruit Feather M0
99 The Adafruit Feather M0 Basic Proto ships with a BOSSA compatible
114 #. Connect the Adafruit Feather M0 Basic Proto to your host computer
153 .. _Adafruit Feather M0 Basic Proto Learn site:
154 https://learn.adafruit.com/adafruit-feather-m0-basic-proto/
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| /Zephyr-latest/samples/subsys/ipc/openamp/remote/ |
| D | sample.yaml | 7 - lpcxpresso54114/lpc54114/m0
10 - lpcxpresso54114/lpc54114/m0
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| /Zephyr-latest/boards/nxp/lpcxpresso54114/ |
| D | lpcxpresso54114_lpc54114_m0.yaml | 7 identifier: lpcxpresso54114/lpc54114/m0
8 name: NXP LPCXpresso54114 M0
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| D | lpcxpresso54114_lpc54114_m0.dts | 20 /*zephyr,console = &flexcomm0; uncomment to use console on M0 */
21 /*zephyr,shell-uart = &flexcomm0; uncomment to use shell on M0 */
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| /Zephyr-latest/samples/drivers/ipm/ipm_mcux/remote/ |
| D | sample.yaml | 8 - lpcxpresso54114/lpc54114/m0
11 - lpcxpresso54114/lpc54114/m0
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| /Zephyr-latest/boards/cypress/cy8ckit_062_wifi_bt/ |
| D | cy8ckit_062_wifi_bt_cy8c6247_m0.yaml | 7 identifier: cy8ckit_062_wifi_bt/cy8c6247/m0
8 name: Cypress PSOC 6 WiFi-BT Pioneer Kit (M0)
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| /Zephyr-latest/samples/bluetooth/hci_uart/dts/arm/nordic/ |
| D | override.dtsi | 4 * ARM Cortex-M0 lowest priority value of 3, i.e. we use it as Zephyr has no
5 * support for ZLI on Cortex-M0.
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| /Zephyr-latest/boards/cypress/cy8ckit_062_ble/ |
| D | cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml | 8 identifier: cy8ckit_062_ble@0.0.0/cy8c6347/m0
9 name: Cypress PSOC 6 BLE Pioneer Kit (M0, rev. 0.0.0)
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| D | cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml | 8 identifier: cy8ckit_062_ble@1.0.0/cy8c6347/m0
9 name: Cypress PSOC 6 BLE Pioneer Kit (M0, rev. 1.0.0)
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| /Zephyr-latest/doc/connectivity/bluetooth/api/mesh/images/ |
| D | dfu_stages_procedures_mesh.svg | 38 <path d="M0 539.17 L508.18 539.17 L508.18 421.14 L0 421.14 L0 539.17 Z" class="st1"/>
53 <path d="M0 539.17 L508.18 539.17 L508.18 128.14 L0 128.14 L0 539.17 Z" class="st1"/>
98 <path d="M0 539.17 L60.31 539.17" class="st7"/>
102 <path d="M0 539.17 L28.5 539.17" class="st7"/>
106 <path d="M0 539.17 L26.46 539.17" class="st7"/>
110 <path d="M0 539.17 L31.02 539.17" class="st7"/>
114 <path d="M0 538.87 L0 525.29 L-361.42 525.29" class="st9"/>
118 <path d="M0 549.37 L0 549.73 L0 805.76 L-309.93 805.76" class="st10"/>
122 <path d="M0 539.17 L0 516.49 L-249.45 516.49" class="st9"/>
130 <path d="M0 532.08 L-51.24 532.08" class="st7"/>
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| D | dfu_roles_mesh.svg | 106 <path d="M0 349.24 L78.02 349.24" class="st8"/>
110 <path d="M0 349.24 L77 349.24" class="st8"/>
114 <path d="M0 349.24 L74.8 349.24" class="st8"/>
118 <path d="M0 349.24 L73.42 349.24" class="st8"/>
122 <path d="M0 349.24 L16.86 349.24" class="st8"/>
126 <path d="M0 349.24 L19.09 349.24" class="st8"/>
130 <path d="M0 349.24 L15.14 349.24" class="st8"/>
134 <path d="M0 349.24 L15.14 349.24" class="st8"/>
138 <path d="M0 349.24 L16.86 349.24" class="st8"/>
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| /Zephyr-latest/include/zephyr/arch/arm/ |
| D | asm_inline_gcc.h | 53 #error "Cortex-M0 and Cortex-M0+ require SoC specific support for cross core synchronisation." in arch_irq_lock()
76 /* On Cortex-M0/M0+, this enables all interrupts if they were not
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| /Zephyr-latest/tests/subsys/llext/src/ |
| D | movwmovt_ext.c | 9 * (except Cortex-M0, M0+ and M1, that don't support them)
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| /Zephyr-latest/samples/subsys/smf/smf_calculator/img/ |
| D | smf_calculator.svg | 9 ><path d="M0 0 L2147483647 0 L2147483647 2147483647 L0 2147483647 L0 0 Z"
12 ><path d="M0 0 L0 20 L20 20 L20 0 Z"
15 ><path d="M0 0 L0 40 L40 40 L40 0 Z"
18 ><path d="M0 0 L0 90 L170 90 L170 0 Z"
21 ><path d="M0 0 L0 90 L190 90 L190 0 Z"
24 ><path d="M0 0 L0 270 L340 270 L340 0 Z"
27 ><path d="M0 0 L0 90 L220 90 L220 0 Z"
30 ><path d="M0 0 L0 90 L290 90 L290 0 Z"
33 ><path d="M0 0 L0 90 L160 90 L160 0 Z"
36 ><path d="M0 0 L0 220 L930 220 L930 0 Z"
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| /Zephyr-latest/soc/nxp/lpc/lpc54xxx/gcc/ |
| D | startup_LPC54114_cm4.S | 32 /* Both the M0+ and M4 core come via this shared startup code,
33 * but the M0+ and M4 core have different vector tables.
47 /* Determine which core (M0+ or M4) this code is running on */
61 /* r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) */
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| /Zephyr-latest/dts/bindings/display/ |
| D | led-strip-matrix.yaml | 117 [M0][M1][M2]
122 [M0][M1][M2]
132 [M2][M1][M0]
137 [M2][M1][M0]
149 [M0][M1][M2]
154 [M0][M1][M2]
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| /Zephyr-latest/soc/infineon/cat1a/psoc6_legacy/ |
| D | cypress_psoc6_dt.h | 23 * because Cortex-M0+ can handle a limited number of interrupts and have
50 * The Cortex-M0+ must get from interrupt parent the interrupt line and
52 * Cortex-M0+ NVIC. The multiplexer is configured by CY_PSOC6_DT_NVIC_MUX_MAP
58 /* Cortex-M0+
76 * since it uses interrupt-parent, and the value at Cortex-M0 NVIC multiplexers
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| /Zephyr-latest/tests/drivers/stepper/drv8424/api/boards/ |
| D | nucleo_f767zi.overlay | 30 "M0",
49 m0-gpios = <&mikroe_stepper_gpios 0 0>;
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| D | mimxrt1060_evk_mimxrt1062_qspi_B.overlay | 30 "M0",
49 m0-gpios = <&mikroe_stepper_gpios 0 0>;
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| /Zephyr-latest/dts/bindings/stepper/ti/ |
| D | ti,drv8424.yaml | 22 m0-gpios = <&mikroe_stepper_gpios 0 0>;
48 m0-gpios:
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![[all …]](/Zephyr/more/Zephyr-latest/samples/subsys/smf/smf_calculator/img/smf_calculator.svg?full=M0){kind=link}