Searched +full:low +full:- +full:frequency (Results 1 – 25 of 431) sorted by relevance
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| /Zephyr-latest/dts/bindings/usb/uac2/ |
| D | zephyr,uac2-channel-cluster.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 front-left:
11 front-right:
15 front-center:
19 low-frequency-effects:
21 description: Low Frequency Effects channel present in the cluster
23 back-left:
27 back-right:
31 front-left-of-center:
35 front-right-of-center:
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| /Zephyr-latest/soc/silabs/ |
| D | Kconfig | 3 # SPDX-License-Identifier: Apache-2.0
18 Set if the Back-Up Real Time Counter (BURTC) HAL module is used.
39 Set if the Ultra Low Energy Timer/Counter (CRYOTIMER) HAL module is used.
54 Set if the Inter-Integrated Circuit Interface (I2C) HAL module is used.
59 Set if the Low Energy Timer (LETIMER) HAL module is used.
64 Set if the Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
217 in on-demand mode, after SoC is initialized.
220 prompt "High Frequency Clock Selection"
224 bool "External high frequency crystal oscillator"
226 Set this option to use the external high frequency crystal oscillator
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| /Zephyr-latest/drivers/clock_control/ |
| D | Kconfig.nrf | 4 # SPDX-License-Identifier: Apache-2.0
48 bool "External low swing"
62 If calibration is disabled when RC is used for low frequency clock then
63 accuracy of the low frequency clock will degrade. Disable on your own
204 int "Frequency request timeout in milliseconds"
208 bool "Request LOW frequency on init"
211 The GDFS service will default to HIGH frequency until it receives
212 a lower frequency request. The NRF2 clock controller drivers
213 expect the clock to be initialized to their lowest frequency, so
218 unnecessary HIGH -> LOW -> HIGH cycle given some module will
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | invensense,icm42670.yaml | 4 # SPDX-License-Identifier: Apache-2.0
6 description: ICM-42670 motion tracking device
8 include: [sensor-device.yaml]
11 int-gpios:
12 type: phandle-array
14 The INT signal default configuration is active-high. The
18 accel-hz:
22 Default frequency of accelerometer. (Unit - Hz)
24 Power-on reset value is 800.
26 - 0
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| D | ti,fdc2x1x.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 sd-gpios:
12 type: phandle-array
18 intb-gpios:
19 type: phandle-array
21 The INTB pin defaults to active low when produced by the sensor.
28 Set to identify the sensor as FDC2114 or FDC2214 (4-channel version)
33 Set the Auto-Scan Mode.
36 "active-channel" (single channel mode).
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| /Zephyr-latest/drivers/led_strip/ |
| D | Kconfig.ws2812 | 4 # SPDX-License-Identifier: Apache-2.0
8 # https://wp.josh.com/2014/05/13/ws2812-neopixels-are-not-so-finicky-once-you-get-to-know-them/
33 # Only an Cortex-M inline assembly implementation for the nRF91, nRF51,
41 controlling with GPIO. The GPIO driver does bit-banging with inline
49 DT_CHOSEN_LED_STRIP := zephyr,led-strip
54 default $(dt_node_int_prop_int,$(DT_CHOSEN_LED_STRIP_PATH),delay-t1h) \
55 if $(dt_node_has_prop,$(DT_CHOSEN_LED_STRIP_PATH),delay-t1h)
56 default $(div,$(mul,700,$(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)),1000000000) \
57 if $(dt_node_has_prop,/cpus/cpu@0,clock-frequency)
63 int "Delay 1 bit low pulse"
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| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ace15_mtpm/ |
| D | adsp_shim.h | 4 * SPDX-License-Identifier: Apache-2.0
41 /* HP RING Oscillator Clock Frequency */
44 /* XTAL Oscillator Clock Frequency */
47 /* LP RING Oscillator Clock Frequency */
50 /* Serial I/O RING Oscillator Clock Frequency */
53 /* High Speed I/O RING Oscillator Clock Frequency */
56 /* Integrated PLL / ROSC Clock Frequency */
62 /* Fabric Clock Frequency Divider */
92 /* Low Power Sequencer DMA Select 0 */
95 /* Low Power Sequencer DMA Select 1 */
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| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ace20_lnl/ |
| D | adsp_shim.h | 4 * SPDX-License-Identifier: Apache-2.0
41 /* HP RING Oscillator Clock Frequency */
44 /* XTAL Oscillator Clock Frequency */
47 /* LP RING Oscillator Clock Frequency */
50 /* Serial I/O RING Oscillator Clock Frequency */
53 /* High Speed I/O RING Oscillator Clock Frequency */
56 /* Integrated PLL / ROSC Clock Frequency */
62 /* Fabric Clock Frequency Divider */
92 /* Low Power Sequencer DMA Select 0 */
95 /* Low Power Sequencer DMA Select 1 */
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| /Zephyr-latest/dts/bindings/can/ |
| D | ti,tcan4x5x.yaml | 2 # SPDX-License-Identifier: Apache-2.0
12 spi-max-frequency = <18000000>;
13 clock-frequency = <40000000>;
14 device-state-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
15 device-wake-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
16 reset-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
17 int-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
18 bosch,mram-cfg = <0x0 15 15 5 5 0 10 10>;
21 can-transceiver {
22 max-bitrate = <8000000>;
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| /Zephyr-latest/dts/bindings/display/ |
| D | istech,ist3931.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: [i2c-device.yaml, display-controller.yaml]
11 reset-gpios:
12 type: phandle-array
17 The RESET pin of IST3931 is active low.
19 as active low.
21 x-offset:
26 y-offset:
31 voltage-converter:
35 voltage-follower:
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| D | sharp,ls0xx.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: [spi-device.yaml, display-controller.yaml]
11 extcomin-gpios:
12 type: phandle-array
18 extcomin-frequency:
20 description: EXTCOMIN pin toggle frequency
22 The frequency with which the EXTCOMIN pin should be toggled. See
23 datasheet of particular display. Higher frequency gives better
24 contrast while low frequency saves power.
26 disp-en-gpios:
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| /Zephyr-latest/dts/bindings/clock/ |
| D | nordic,nrf-auxpll.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The output frequency (f_out) of the auxiliary PLL is calculated as follows:
9 f_out = ((R + A * 2^(-16)) * f_src) / B
13 - A: nordic,frequency
14 - B: nordic,outdiv
15 - R: nordic,range (3=low, 4=mid, 5=high, 6=statichigh)
16 - f_src: Source frequency, given by clocks
18 compatible: "nordic,nrf-auxpll"
21 - base.yaml
22 - clock-controller.yaml
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| D | nordic,nrf54h-lfxo.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Nordic nRF54H Series low-frequency crystal oscillator
6 compatible: "nordic,nrf54h-lfxo"
8 include: fixed-clock.yaml
11 clock-frequency:
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| D | nordic,nrf53-lfxo.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Nordic nRF low-frequency crystal oscillator (nRF53 series)
6 compatible: "nordic,nrf53-lfxo"
8 include: fixed-clock.yaml
11 clock-frequency:
14 load-capacitors:
17 - "internal"
18 - "external"
22 load-capacitance-picofarad:
25 - 6
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| /Zephyr-latest/samples/boards/nordic/clock_control/ |
| D | Kconfig | 2 # SPDX-License-Identifier: Apache-2.0
5 int "Frequency specification to request from clock in Hz"
8 0 -> ignore frequency
9 >0 -> use at minimum selected frequency. To select the
10 highest supported frequency use UINT32_MAX.
16 0 -> ignore accuracy
17 1 -> use max accuracy
18 >1 -> use at minimum selected accuracy
24 0 -> low precision
25 1 -> high precision
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| /Zephyr-latest/boards/st/nucleo_wba55cg/support/ |
| D | openocd.cfg | 4 source [find interface/stlink-dap.cfg]
10 # Enable debug when in low power modes
16 # STlink Debug clock frequency
21 # connect_assert_srst needed if low power mode application running (WFI...)
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| /Zephyr-latest/dts/bindings/rtc/ |
| D | microcrystal,rv3028.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 - name: rtc-device.yaml
10 - name: i2c-device.yaml
13 clkout-frequency:
16 - 32768
17 - 8192
18 - 1024
19 - 64
20 - 32
21 - 1
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| /Zephyr-latest/doc/hardware/peripherals/sensor/ |
| D | device_tree.rst | 10 .. code-block:: dts
12 #include <zephyr/dt-bindings/icm42688.h>
20 … int-gpios = <&pioc 6 GPIO_ACTIVE_HIGH>; /* SoC specific pin to select for interrupt line */
21 spi-max-frequency = <DT_FREQ_M(24)>; /* Maximum SPI bus frequency */
22 accel-pwr-mode = <ICM42688_ACCEL_LN>; /* Low noise mode */
23 accel-odr = <ICM42688_ACCEL_ODR_2000>; /* 2000 Hz sampling */
24 accel-fs = <ICM42688_ACCEL_FS_16>; /* 16G scale */
25 gyro-pwr-mode = <ICM42688_GYRO_LN>; /* Low noise mode */
26 gyro-odr = <ICM42688_GYRO_ODR_2000>; /* 2000 Hz sampling */
27 gyro-fs = <ICM42688_GYRO_FS_16>; /* 16G scale */
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| /Zephyr-latest/boards/st/nucleo_wba52cg/support/ |
| D | openocd.cfg | 4 source [find interface/stlink-dap.cfg]
10 # Enable debug when in low power modes
16 # STlink Debug clock frequency
21 # connect_assert_srst needed if low power mode application running (WFI...)
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| /Zephyr-latest/dts/bindings/timer/ |
| D | nuclei,systimer.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Nuclei system timer provides RISC-V privileged mtime and mtimecmp
21 clk-divider:
24 clk-divider specifies the division ratio to the CPU frequency that
28 This configuration is used sometimes for such as low power consumption.
30 For example, the CPU clock frequency is 108MHz, and the system timer
32 In this case, the CPU clock frequency is defined in the CPU node
35 clock-frequency = <108000000>;
38 The relationship with the frequency division ratio is as
44 Setting clk-divider to 2 specifies the system timer uses the clock
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| /Zephyr-latest/dts/bindings/counter/ |
| D | nxp,lptmr.yaml | 2 # SPDX-License-Identifier: Apache-2.0
14 clock-frequency:
16 description: Counter clock frequency
20 description: The frequency of the counter is divided by this value.
22 clk-source:
33 input-pin:
37 will be used to determine the "rising-edge
40 active-low:
44 will set the counter to active low.
51 prescale-glitch-filter:
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| /Zephyr-latest/tests/boards/nrf/i2c/i2c_slave/boards/ |
| D | nrf54h20dk_nrf54h20_cpuapp.overlay | 3 i2c-slave = &i2c131;
19 low-power-enable;
29 bias-pull-up;
37 low-power-enable;
43 compatible = "nordic,nrf-twim";
45 clock-frequency = <I2C_BITRATE_STANDARD>;
46 pinctrl-0 = <&i2c130_default_alt>;
47 pinctrl-1 = <&i2c130_sleep_alt>;
48 pinctrl-names = "default", "sleep";
49 memory-regions = <&cpuapp_dma_region>;
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| D | nrf54h20dk_nrf54h20_cpuppr.overlay | 3 i2c-slave = &i2c131;
19 low-power-enable;
30 bias-pull-up;
38 low-power-enable;
44 compatible = "nordic,nrf-twim";
46 clock-frequency = <I2C_BITRATE_STANDARD>;
47 pinctrl-0 = <&i2c130_default_alt>;
48 pinctrl-1 = <&i2c130_sleep_alt>;
49 pinctrl-names = "default", "sleep";
56 compatible = "nordic,nrf-twis";
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| /Zephyr-latest/soc/nordic/nrf54h/bicr/ |
| D | bicr-schema.json | 14 "VDDH supplied with 2.1-5.5 V and VDD regulated by the chip (inductor present)",
155 "title": "Low Frequency Oscillator (LFOSC) configuration",
161 "Low Frequency Crystal Oscillator (LFXO)",
162 "Low Frequency RC Oscillator (LFRC)"
184 "title": "Low Frequency Crystal Oscillator (LFXO) configuration",
240 "title": "Use built-in load capacitors",
257 "title": "Built-in load capacitance",
285 "title": "Low Frequency RC (LFRC) autocalibration configuration",
347 "title": "High Frequency Cristal Oscillator (HFXO) configuration",
385 "title": "Use built-in load capacitors",
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| /Zephyr-latest/soc/nxp/kinetis/ |
| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
33 bool "Low power oscillator"
35 Set this option to use the oscillator in low-power mode.
40 Set this option to use the oscillator in high-gain mode.
45 int "External oscillator frequency"
47 Set the external oscillator frequency in Hz. This should be set by the
60 The resulting frequency must be in the range of 2 MHz to 4 MHz.
69 frequency.
77 resulting frequency must be in the range 31.25 kHz to 4 MHz.
85 FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625
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