Searched full:hsisys (Results 1 – 4 of 4) sorted by relevance
8 It also produces a HSISYS secondary clk which can be used as system clock12 - 1 ==> HSISYS = 48MHZ13 - 2 ==> HSISYS = 24MHZ14 - 4 ==> HSISYS = 12MHZ15 - 8 ==> HSISYS = 6MHZ16 - 16 ==> HSISYS = 3MHZ17 - 32 ==> HSISYS = 1.5MHz18 - 64 ==> HSISYS = 0.75MHZ19 - 128 ==> HSISYS = 0.375MHz30 HSI clock divider. Configures the output HSI clock frequency (HSISYS).
8 It also produces a HSISYS secondary clk which can be used as system clock12 - 1 ==> HSISYS = 16MHZ13 - 2 ==> HSISYS = 8MHZ14 - 4 ==> HSISYS = 4MHZ15 - 8 ==> HSISYS = 2MHZ16 - 16 ==> HSISYS = 1MHZ17 - 32 ==> HSISYS = 0.5MHz18 - 64 ==> HSISYS = 0.25MHZ19 - 128 ==> HSISYS = 0.125MHz30 HSI clock divider. Configures the output HSI clock frequency (HSISYS),
15 hsi-div = <2>; /* HSISYS = 8Mhz */
15 hsi-div = <4>; /* HSISYS = 4Mhz */
