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/Zephyr-latest/drivers/clock_control/
Dclock_control_npcm.c48 volatile uint8_t hfcbcd1; member
353 priv->hfcbcd1 = (I3CDIV_VAL << 2) | FIUDIV_VAL; in npcm_clock_control_init()
Dclock_control_npcx.c235 inst_cdcg->HFCBCD1 = VAL_HFCBCD1; in npcx_clock_control_init()
/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcm-pcc.yaml198 programmable divider controlled by the FIUDIV field in HFCBCD1 register.
/Zephyr-latest/soc/nuvoton/npcx/common/reg/
Dreg_def.h77 volatile uint8_t HFCBCD1; member