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/Zephyr-latest/boards/nxp/imx93_evk/
Dimx93_evk_mimx9352_m33.dts36 gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
40 gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
44 gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
53 gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
59 gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
76 &gpio2 {
Dimx93_evk_mimx9352_a55.dts45 gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
49 gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
53 gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
62 gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
68 gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
188 &gpio2{
/Zephyr-latest/boards/adi/max32690fthr/
Dmax32690fthr_max32690_m4.dts32 gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
36 gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
74 <6 0 &gpio2 29 0>, /* SCK */
75 <7 0 &gpio2 28 0>, /* MOSI */
76 <8 0 &gpio2 27 0>, /* MISO */
80 <12 0 &gpio2 7 0>, /* SDA */
81 <13 0 &gpio2 8 0>, /* SCL */
84 <16 0 &gpio2 26 0>, /* D9 */
104 &gpio2 {
/Zephyr-latest/boards/adi/max32655fthr/
Dmax32655fthr_max32655_m4.dts88 <10 0 &gpio2 7 0>, /* TX */
89 <9 0 &gpio2 6 0>, /* RX */
93 <5 0 &gpio2 5 0>, /* AIN5 */
94 <4 0 &gpio2 4 0>, /* AIN4 */
95 <3 0 &gpio2 3 0>, /* AIN3 */
96 <2 0 &gpio2 2 0>, /* AIN2 */
97 <1 0 &gpio2 1 0>, /* AIN1 */
98 <0 0 &gpio2 0 0>; /* AIN0 */
130 &gpio2 {
/Zephyr-latest/tests/drivers/stepper/drv8424/emul/boards/
Dnative_sim.overlay16 sleep-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* D2 */
17 en-gpios = <&gpio2 1 0>; /* 5 */
34 gpio2: gpio2 {
/Zephyr-latest/tests/drivers/stepper/drv8424/api/boards/
Dnative_sim.overlay16 sleep-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* D2 */
17 en-gpios = <&gpio2 1 0>; /* 5 */
34 gpio2: gpio2 {
/Zephyr-latest/boards/infineon/xmc47_relax_kit/
Darduino_r3_connector.dtsi18 <6 0 &gpio2 15 0>, /* D0 */
19 <7 0 &gpio2 14 0>, /* D1 */
23 <11 0 &gpio2 12 0>, /* D5 */
24 <12 0 &gpio2 11 0>, /* D6 */
45 &gpio2 {
/Zephyr-latest/samples/sensor/qdec/boards/
Dnrf54h20dk_nrf54h20_cpuapp.overlay16 gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
19 gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
33 &gpio2 {
/Zephyr-latest/boards/nxp/lpcxpresso11u68/
Dlpcxpresso11u68.dts50 gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
54 gpios = <&gpio2 17 GPIO_ACTIVE_LOW>;
58 gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
74 <6 0 &gpio2 11 0>, /* D0 */
75 <7 0 &gpio2 12 0>, /* D1 */
83 <15 0 &gpio2 3 0>, /* D9 */
127 &gpio2 {
/Zephyr-latest/dts/bindings/gpio/
Dxlnx,xps-gpio-1.00.a.yaml44 1 if controller has GPIO2 enabled, 0 otherwise
59 Default output value. If n-th bit is 1, GPIO2-n default value is 1.
61 xlnx,gpio2-width:
69 Default tristate register value. If n-th bit is 1, GPIO2-n is an input.
Dxlnx,xps-gpio-1.00.a-gpio2.yaml1 description: Xilinx AXI GPIO IP GPIO2 node
3 compatible: "xlnx,xps-gpio-1.00.a-gpio2"
/Zephyr-latest/boards/silabs/dev_kits/sim3u1xx_dk/
Dsim3u1xx_dk.dts36 gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
40 gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
49 gpios = <&gpio2 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
54 gpios = <&gpio2 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
90 &gpio2 {
/Zephyr-latest/boards/adi/max78002evkit/
Dmax78002evkit_max78002_m4.dts28 gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
32 gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
40 gpios = <&gpio2 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
45 gpios = <&gpio2 7 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
92 &gpio2 {
/Zephyr-latest/tests/drivers/gpio/gpio_basic_api/boards/
Dimx93_evk_mimx9352_a55.overlay10 out-gpios = <&gpio2 13 0>;
11 in-gpios = <&gpio2 14 0>;
Dmax32680evkit_max32680_m4.overlay10 out-gpios = <&gpio2 6 0>;
11 in-gpios = <&gpio2 7 0>;
Dmax32655evkit_max32655_m4.overlay10 out-gpios = <&gpio2 0 0>;
11 in-gpios = <&gpio2 1 0>;
Dmax32690evkit_max32690_m4.overlay10 out-gpios = <&gpio2 7 0>;
11 in-gpios = <&gpio2 8 0>;
Dmax32655fthr_max32655_m4.overlay10 out-gpios = <&gpio2 0 0>;
11 in-gpios = <&gpio2 1 0>;
/Zephyr-latest/tests/boards/nrf/qdec/boards/
Dnrf54h20dk_nrf54h20_cpuapp.overlay16 gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
19 gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
41 &gpio2 {
/Zephyr-latest/boards/adi/apard32690/
Dapard32690_max32690_m4.dts28 gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
68 <6 0 &gpio2 14 0>, /* D0 */
69 <7 0 &gpio2 16 0>, /* D1 */
70 <8 0 &gpio2 13 0>, /* D2 */
71 <9 0 &gpio2 15 0>, /* D3 */
82 <20 0 &gpio2 17 0>, /* D14 */
83 <21 0 &gpio2 18 0>; /* D15 */
103 &gpio2 {
/Zephyr-latest/boards/snps/em_starterkit/
Dboard.dtsi85 gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
91 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
97 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
103 gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
/Zephyr-latest/boards/microchip/mpfs_icicle/
Dmpfs_icicle_common.dtsi26 gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
34 gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
71 &gpio2 {
/Zephyr-latest/boards/adi/max32690evkit/
Dmax32690evkit_max32690_m4.dts34 gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
94 clk-gpios = <&gpio2 25 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>;
95 mosi-gpios = <&gpio2 24 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>;
96 cs-gpios = <&gpio2 11 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>;
116 &gpio2 {
/Zephyr-latest/tests/drivers/uart/uart_async_api/boards/
Desp32c6_devkitc.overlay11 input-enable; /* Connect GPIO2 and GPIO3 externally for testing */
15 output-enable; /* Connect GPIO2 and GPIO3 externally for testing */
/Zephyr-latest/boards/nxp/vmu_rt1170/
Dvmu_rt1170_mimxrt1176_cm7.dts56 enable-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
65 enable-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
74 enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
104 enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
114 enable-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
141 &gpio2 {
250 cs-gpios =<&gpio2 11 GPIO_ACTIVE_LOW>;
273 int-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
286 cs-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>,
287 <&gpio2 18 GPIO_ACTIVE_LOW>;
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