| /Zephyr-latest/drivers/gpio/ |
| D | Kconfig | 1 # GPIO configuration options
6 menuconfig GPIO config
7 bool "General-Purpose Input/Output (GPIO) drivers"
9 Include GPIO drivers in system config
11 if GPIO
13 module = GPIO
14 module-str = gpio
18 bool "GPIO Shell"
21 Enable GPIO Shell for testing.
24 bool "GPIO Shell info command"
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| D | gpio_sam4l.c | 15 #include <zephyr/drivers/gpio.h>
19 #include <zephyr/drivers/gpio/gpio_utils.h>
26 Gpio *regs;
45 Gpio * const gpio = cfg->regs; in gpio_sam_port_configure() local
53 gpio->IERC = mask; in gpio_sam_port_configure()
54 gpio->PUERC = mask; in gpio_sam_port_configure()
55 gpio->PDERC = mask; in gpio_sam_port_configure()
56 gpio->GPERS = mask; in gpio_sam_port_configure()
57 gpio->ODERC = mask; in gpio_sam_port_configure()
58 gpio->STERC = mask; in gpio_sam_port_configure()
[all …]
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| /Zephyr-latest/soc/atmel/sam/common/ |
| D | soc_sam4l_gpio.c | 7 * @brief Atmel SAM MCU family General-Purpose Input/Output Controller (GPIO)
14 static void configure_common_attr(volatile Gpio *gpio, in configure_common_attr() argument
20 gpio->IERC = mask; in configure_common_attr()
24 gpio->PUERS = mask; in configure_common_attr()
26 gpio->PUERC = mask; in configure_common_attr()
31 gpio->PDERS = mask; in configure_common_attr()
33 gpio->PDERC = mask; in configure_common_attr()
38 gpio->ODMERS = mask; in configure_common_attr()
40 gpio->ODMERC = mask; in configure_common_attr()
44 static void configure_input_attr(volatile Gpio *gpio, in configure_input_attr() argument
[all …]
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | m5stack,stamps3-header.yaml | 5 GPIO pins exposed on M5Stack StampS3 module headers.
9 0 GPIO
10 1 GPIO
11 2 GPIO/CLKOUT0
12 3 GPIO
13 4 GPIO/SPILCD
14 5 GPIO/SPILCD
15 6 GPIO/SPILCD 27 3V3
16 7 GPIO 26 GPIO
17 8 GPIO/CLKOUT0 25 GPIO/CLKOUT/TXD
[all …]
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| D | ambiq,gpio.yaml | 5 Ambiq GPIO provides the GPIO pin mapping for GPIO child nodes.
7 The Ambiq Apollo4x soc designs a single GPIO port with 128 pins.
8 It uses 128 continuous 32-bit registers to configure the GPIO pins.
10 32 pins handling in GPIO driver API.
12 The Ambiq Apollo4x soc should define one "ambiq,gpio" parent node in soc
13 devicetree and some child nodes which are compatible with "ambiq,gpio-bank"
16 Here is an example of how a "ambiq,gpio" node can be used with the combined
17 gpio child nodes:
19 gpio: gpio@40010000 {
20 compatible = "ambiq,gpio";
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| D | ti,boosterpack-header.yaml | 5 TI BoosterPack GPIO header
7 GPIO pins exposed as BoosterPack headers on TI LaunchPads.
17 1 3.3V 21 5V 40 GPIO 20 GND
18 2 Analog 22 GND 39 GPIO 19 GPIO / SPI CS
19 3 UART RXD 23 Analog 38 GPIO 18 GPIO
20 4 UART TXD 24 Analog 37 GPIO 17 GPIO
21 5 GPIO 25 Analog 36 GPIO 16 RESET
22 6 Analog 26 Analog 35 GPIO 15 SPI MOSI
23 7 SPI CLK 27 Analog 34 GPIO 14 SPI MISO
24 8 GPIO 28 Analog 33 GPIO 13 GPIO / SPI CS
[all …]
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| D | nuvoton,nct38xx-gpio.yaml | 5 Nuvoton NCT38XX series I2C-based GPIO expander
15 nct3807-gpio {
18 compatible = "nuvoton,nct38xx-gpio";
20 gpio@0 {
21 compatible = "nuvoton,nct38xx-gpio-port";
23 gpio-controller;
24 #gpio-cells = <2>;
30 gpio@1 {
31 compatible = "nuvoton,nct38xx-gpio-port";
33 gpio-controller;
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| D | gpio-controller.yaml | 4 # Common fields for GPIO controllers
7 "gpio-controller":
10 description: Convey's this node is a GPIO controller
11 "#gpio-cells":
14 description: Number of items to expect in a GPIO specifier
28 gpio-reserved-ranges:
36 For example, setting "gpio-reserved-ranges = <3 2>, <10 1>;" means that
37 GPIO offsets 3, 4, and 10 are not usable, even if ngpios = <18>.
38 gpio-line-names:
41 This is an array of strings defining the names of the GPIO lines
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| D | nxp,s32-gpio.yaml | 5 NXP S32 GPIO controller.
7 The GPIO controller provides the option to route external input pad interrupts
9 the WKPU interrupt controller. By default, GPIO interrupts are routed to the
12 To route external interrupts to the WKPU interrupt controller, the GPIO
14 the following snippet of devicetree source code instructs the GPIO controller
17 #include <zephyr/dt-bindings/gpio/nxp-s32-gpio.h>
23 Explicitly specifying the routing of a GPIO interrupt to a particular
34 as the interrupt controller for the corresponding GPIO. It's worth noting that
38 compatible: "nxp,s32-gpio"
40 include: [gpio-controller.yaml, base.yaml]
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| /Zephyr-latest/dts/x86/intel/ |
| D | gpio_common.dtsi | 9 #include <zephyr/dt-bindings/gpio/gpio.h>
14 compatible = "intel,gpio";
17 gpio-controller;
18 #gpio-cells = <2>;
23 compatible = "intel,gpio";
26 gpio-controller;
27 #gpio-cells = <2>;
32 compatible = "intel,gpio";
35 gpio-controller;
36 #gpio-cells = <2>;
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| /Zephyr-latest/tests/drivers/gpio/gpio_reserved_ranges/boards/ |
| D | native_posix.overlay | 9 compatible = "test-gpio-reserved-ranges";
14 test_gpio_1: gpio@deadbeef {
15 compatible = "vnd,gpio-device";
16 gpio-controller;
18 #gpio-cells = < 0x2 >;
21 gpio-reserved-ranges = <0 4>, <5 3>, <9 5>, <11 2>,
26 test_gpio_2: gpio@abcd1234 {
27 compatible = "vnd,gpio-device";
28 gpio-controller;
30 #gpio-cells = < 0x2 >;
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| /Zephyr-latest/dts/arm/renesas/rz/rzg/ |
| D | r9a08g045.dtsi | 40 gpio: gpio-common { label
41 compatible = "renesas,rz-gpio-int";
55 gpio0: gpio@0 {
56 compatible = "renesas,rz-gpio";
57 gpio-controller;
58 #gpio-cells = <2>;
64 gpio1: gpio@1000 {
65 compatible = "renesas,rz-gpio";
66 gpio-controller;
67 #gpio-cells= <2>;
[all …]
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| /Zephyr-latest/boards/m5stack/m5stack_cores3/ |
| D | m5stack_mbus_connectors.dtsi | 9 #gpio-cells = <2>;
10 gpio-map-mask = <0xffffffff 0xffffffc0>;
11 gpio-map-pass-thru = <0 0x3f>;
12 gpio-map = /* GND */ <1 0 &gpio 10 0>, /* ADC */
13 /* GND */ <3 0 &gpio 8 0>, /* PB_IN */
15 /* MOSI */ <6 0 &gpio 37 0>, <7 0 &gpio 5 0>, /* GPIO */
16 /* MISO */ <8 0 &gpio 35 0>, <9 0 &gpio 9 0>, /* PB_OUT */
17 /* SCK */ <10 0 &gpio 36 0>, /* 3.3V */
18 /* RXD0 */ <12 0 &gpio 44 0>, <13 0 &gpio 43 0>, /* TXD0 */
19 /* PC_RX */ <14 0 &gpio 18 0>, <15 0 &gpio 17 0>, /* PC_TX */
[all …]
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| /Zephyr-latest/tests/drivers/build_all/gpio/ |
| D | app.overlay | 18 test_gpio: gpio@deadbeef {
19 compatible = "vnd,gpio";
20 gpio-controller;
22 #gpio-cells = <0x2>;
26 test_gpio_dw: gpio@c0ffee {
27 compatible = "snps,designware-gpio";
28 gpio-controller;
30 #gpio-cells = <0x2>;
45 #gpio-cells = <2>;
47 gpio-controller;
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| D | testcase.yaml | 5 - gpio
7 drivers.gpio.build:
11 - gpio
15 drivers.gpio.build.efinix_sapphire:
18 depends_on: gpio
21 drivers.gpio.build.altera_pio:
26 depends_on: gpio
29 drivers.gpio.build.adc_ads1145s0x_gpio:
39 - gpio
49 drivers.gpio.build.adc_lmp90xxx_gpio:
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| /Zephyr-latest/tests/drivers/gpio/gpio_basic_api/boards/ |
| D | intel_ehl_crb.overlay | 6 /* By default, EHL_CRB on SBL, SBL locks all gpio registeration configuration.
8 * GPIO Settings -> GPIO_GPP_B -> GPP_B04 -> GPIO Skip -> Disable
9 * GPIO Settings -> GPIO_GPP_B -> GPP_B04 -> PadMode -> GPIO control of the pad
10 * GPIO Settings -> GPIO_GPP_B -> GPP_B04 -> HostSoftPadOwn -> Host ownership to GPIO Driver mode
11 * GPIO Settings -> GPIO_GPP_B -> GPP_B04 -> Direction -> DirOut
12 * GPIO Settings -> GPIO_GPP_B -> GPP_B04 -> LockConfig -> PadUnlock
13 * GPIO Settings -> GPIO_GPP_B -> GPP_B23 -> GPIO Skip -> Disable
14 * GPIO Settings -> GPIO_GPP_B -> GPP_B23 -> PadMode -> GPIO control of the pad
15 * GPIO Settings -> GPIO_GPP_B -> GPP_B23 -> HostSoftPadOwn -> Host ownership to GPIO Driver mode
16 * GPIO Settings -> GPIO_GPP_B -> GPP_B23 -> Direction -> DirIn
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| /Zephyr-latest/boards/m5stack/m5stack_stamps3/ |
| D | m5stack_stamps3_connectors.dtsi | 9 #gpio-cells = <2>;
10 gpio-map-mask = <0xffffffff 0xffffffc0>;
11 gpio-map-pass-thru = <0 0x3f>;
12 gpio-map =
13 <0 0 &gpio0 1 0>, /* GPIO/AIN */
14 <1 0 &gpio0 2 0>, /* GPIO/AIN */
15 <2 0 &gpio0 3 0>, /* GPIO/AIN/CLKOUT1-3 */
16 <3 0 &gpio0 4 0>, /* GPIO/AIN */
17 <4 0 &gpio0 5 0>, /* GPIO/AIN/SPI2-MOSI */
18 <5 0 &gpio0 6 0>, /* GPIO/AIN/SPI2-CLK */
[all …]
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| /Zephyr-latest/dts/arm/infineon/cat1a/psoc6_04/ |
| D | psoc6_04.dtsi | 66 gpio_prt0: gpio@40310000 {
67 compatible = "infineon,cat1-gpio";
70 gpio-controller;
73 #gpio-cells = <2>;
75 gpio_prt1: gpio@40310080 {
76 compatible = "infineon,cat1-gpio";
78 gpio-controller;
81 #gpio-cells = <2>;
83 gpio_prt2: gpio@40310100 {
84 compatible = "infineon,cat1-gpio";
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| /Zephyr-latest/include/zephyr/devicetree/ |
| D | gpio.h | 3 * @brief GPIO Devicetree macro public API header file.
21 * @defgroup devicetree-gpio Devicetree GPIO API
28 * gpio phandle-array property at an index
32 * gpio1: gpio@... { };
34 * gpio2: gpio@... { };
46 * @param gpio_pha lowercase-and-underscores GPIO property with
49 * @return the node identifier for the gpio controller referenced at
59 * @param gpio_pha lowercase-and-underscores GPIO property with
61 * @return a node identifier for the gpio controller at index 0
69 * @brief Get a GPIO specifier's pin cell at an index
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| /Zephyr-latest/boards/96boards/nitrogen/ |
| D | 96b_lscon.dtsi | 10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <23 0 &gpio0 2 0>, /* GPIO-A */
14 <24 0 &gpio0 3 0>, /* GPIO-B */
15 <25 0 &gpio0 4 0>, /* GPIO-C */
16 <26 0 &gpio0 5 0>, /* GPIO-D */
17 <27 0 &gpio0 6 0>, /* GPIO-E */
18 <28 0 &gpio0 7 0>, /* GPIO-F */
19 <29 0 &gpio0 8 0>, /* GPIO-G */
[all …]
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| /Zephyr-latest/dts/arm/nuvoton/ |
| D | m48x.dtsi | 9 #include <zephyr/dt-bindings/gpio/gpio.h>
48 gpioa: gpio@40004000 {
49 compatible = "nuvoton,numicro-gpio";
53 gpio-controller;
54 #gpio-cells = <2>;
58 gpiob: gpio@40004040 {
59 compatible = "nuvoton,numicro-gpio";
63 gpio-controller;
64 #gpio-cells = <2>;
68 gpioc: gpio@40004080 {
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| /Zephyr-latest/dts/arm/infineon/cat1a/psoc6_03/ |
| D | psoc6_03.dtsi | 66 gpio_prt0: gpio@40310000 {
67 compatible = "infineon,cat1-gpio";
70 gpio-controller;
73 #gpio-cells = <2>;
75 gpio_prt2: gpio@40310100 {
76 compatible = "infineon,cat1-gpio";
79 gpio-controller;
82 #gpio-cells = <2>;
84 gpio_prt3: gpio@40310180 {
85 compatible = "infineon,cat1-gpio";
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| /Zephyr-latest/tests/drivers/gpio/gpio_basic_api/ |
| D | testcase.yaml | 4 - gpio
5 depends_on: gpio
11 drivers.gpio.2pin:
13 filter: dt_compat_enabled("test-gpio-basic-api") and not dt_compat_enabled("arduino-header-r3")
15 drivers.gpio.nrf_sense_edge:
27 drivers.gpio.mr_canhubk3_wkpu:
31 drivers.gpio.2pin_ke17z_fgpio:
33 filter: dt_compat_enabled("test-gpio-basic-api")
41 drivers.gpio.2pin_arduino:
44 - gpio
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| /Zephyr-latest/dts/arm/ti/ |
| D | lm3s6965.dtsi | 74 gpio0: gpio@40004000 {
75 compatible = "ti,stellaris-gpio";
78 gpio-controller;
79 #gpio-cells = <2>;
83 gpio1: gpio@40005000 {
84 compatible = "ti,stellaris-gpio";
87 gpio-controller;
88 #gpio-cells = <2>;
92 gpio2: gpio@40006000 {
93 compatible = "ti,stellaris-gpio";
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| /Zephyr-latest/tests/drivers/gpio/gpio_api_1pin/ |
| D | testcase.yaml | 4 - gpio
5 depends_on: gpio
8 drivers.gpio.1pin:
10 dt_enabled_alias_with_parent_compat("led0", "gpio-leds")
11 and not dt_compat_enabled("test-gpio-external-pulldown")
17 drivers.gpio.1pin.aw9523b:
20 - gpio
22 - gpio
29 filter: dt_enabled_alias_with_parent_compat("led0", "gpio-leds") and
33 drivers.gpio.1pin.external_pull_down:
[all …]
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