Lines Matching full:gpio
5 Ambiq GPIO provides the GPIO pin mapping for GPIO child nodes.
7 The Ambiq Apollo4x soc designs a single GPIO port with 128 pins.
8 It uses 128 continuous 32-bit registers to configure the GPIO pins.
10 32 pins handling in GPIO driver API.
12 The Ambiq Apollo4x soc should define one "ambiq,gpio" parent node in soc
13 devicetree and some child nodes which are compatible with "ambiq,gpio-bank"
16 Here is an example of how a "ambiq,gpio" node can be used with the combined
17 gpio child nodes:
19 gpio: gpio@40010000 {
20 compatible = "ambiq,gpio";
21 gpio-map-mask = <0xffffffe0 0xffffffc0>;
22 gpio-map-pass-thru = <0x1f 0x3f>;
23 gpio-map = <
30 #gpio-cells = <2>;
36 compatible = "ambiq,gpio-bank";
37 gpio-controller;
38 #gpio-cells = <2>;
45 compatible = "ambiq,gpio-bank";
46 gpio-controller;
47 #gpio-cells = <2>;
54 compatible = "ambiq,gpio-bank";
55 gpio-controller;
56 #gpio-cells = <2>;
63 compatible = "ambiq,gpio-bank";
64 gpio-controller;
65 #gpio-cells = <2>;
72 In the above example, the gpio@40010000 is a "ambiq,gpio" parent node which
73 provides the base register address 0x40010000. It has four "ambiq,gpio-bank"
76 address offset. The register address of pin described in gpio-cells can be
79 = 0x400100D0 and the real GPIO pin number of this pin in soc is (20 + 32)
82 compatible: "ambiq,gpio"
84 include: [gpio-nexus.yaml, base.yaml]