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/Zephyr-latest/drivers/fpga/
DKconfig1 # FPGA driver configuration options
6 menuconfig FPGA config
7 bool "Field-Programmable Gate Array (FPGA) drivers"
9 Enable support for FPGA drivers.
11 if FPGA
13 module = FPGA
14 module-str = fpga
21 FPGA device drivers initialization priority
24 bool "FPGA Shell"
25 depends on SHELL && FPGA
[all …]
DKconfig.ice405 bool "Lattice iCE40 fpga driver"
12 Enable support for the Lattice iCE40 fpga driver.
17 bool "Lattice iCE40 fpga SPI driver"
21 Enable support for the Lattice iCE40 fpga SPI driver.
24 bool "Lattice iCE40 fpga driver GPIO bitbang"
29 Enable support for the Lattice iCE40 fpga GPIO bitbang driver.
DKconfig.altera_agilex_bridge1 # FPGA ALTERA driver configuration options
7 bool "ALTERA fpga driver"
10 Enable ALTERA FPGA driver.
DKconfig.eos_s31 # FPGA EOS S3 driver configuration options
7 bool "EOS S3 fpga driver"
9 Enable EOS S3 FPGA driver.
DKconfig.zynqmp1 # FPGA ZYNQMP driver configuration options
7 bool "ZYNQMP fpga driver"
9 Enable ZYNQMP FPGA driver.
DKconfig.mpfs1 # FPGA Microchip PolarFire SOC driver configuration options
7 bool "Microchip PolarFire SOC FPGA driver"
10 Enable support for the Microchip PolarFire SOC FPGA driver.
Dfpga_eos_s3.c10 #include <zephyr/drivers/fpga.h>
57 /* wake up the FPGA power domain */ in eos_s3_fpga_on()
60 /* The register will clear itself if the FPGA starts */ in eos_s3_fpga_on()
65 /* enable FPGA programming */ in eos_s3_fpga_on()
114 /* disable FPGA programming */ in eos_s3_fpga_load()
143 static DEVICE_API(fpga, eos_s3_api) = {
/Zephyr-latest/samples/drivers/fpga/fpga_controller/
DREADME.rst1 .. zephyr:code-sample:: fpga-controller
2 :name: FPGA Controller
4 Load a bitstream into an FPGA and perform basic operations on it.
8 This module is an FPGA driver that can easily load a bitstream, reset it, check its status, enable …
9 This sample demonstrates how to use the FPGA driver API and the FPGA controller shell subsystem.
26 :zephyr-app: samples/drivers/fpga/fpga_controller
32 To build the FPGA Controller shell application, use the supplied
36 :zephyr-app: samples/drivers/fpga/fpga_controller
54 For the FPGA controller shell application, after connecting to the shell console you should see the…
68 The FPGA controller command can now be used (``fpga load <device> <address> <size in bytes>``):
[all …]
Dsample.yaml2 name: FPGA Controller sample
5 tags: FPGA
/Zephyr-latest/boards/digilent/arty_a7/doc/
Dindex.rst9 The `Digilent Arty`_ is a line of FPGA-based development boards aimed for makers
11 different Xilinx FPGA (Spartan-7, Artix-7, or Zynq-7000 series).
13 Each board is equipped with on-board JTAG for FPGA programming and debugging,
14 LEDs, switches, buttons, DDR3 RAM, and QSPI flash for storing the FPGA
24 so-called soft processor to be instantiated within the FPGA in order to run
27 ARM Cortex-M1/M3 DesignStart FPGA
31 DesignStart FPGA`_ Xilinx edition reference designs from ARM. Zephyr supports
37 For more information about the ARM Cortex-M1/M3 DesignStart FPGA, see the
40 - `Technical Resources for DesignStart FPGA`_
41 - `Technical Resources for DesignStart FPGA on Xilinx`_
[all …]
/Zephyr-latest/include/zephyr/drivers/
Dfpga.h21 /* Inactive is when the FPGA cannot accept the bitstream
25 /* Active is when the FPGA can accept the bitstream and
49 * @brief Read the status of FPGA.
51 * @param dev FPGA device structure.
53 * @retval 0 if the FPGA is in INACTIVE state.
54 * @retval 1 if the FPGA is in ACTIVE state.
72 * @brief Reset the FPGA.
74 * @param dev FPGA device structure.
92 * @brief Load the bitstream and program the FPGA
94 * @param dev FPGA device structure.
[all …]
/Zephyr-latest/samples/drivers/fpga/fpga_controller/src/
Dmain.c11 #include <zephyr/drivers/fpga.h>
16 const struct device *const fpga = DEVICE_DT_GET(DT_NODELABEL(fpga0)); variable
34 if (!device_is_ready(fpga)) { in main()
35 printk("fpga device is not ready\n"); in main()
39 fpga_load(fpga, axFPGABitStream_red, in main()
42 fpga_reset(fpga); in main()
43 fpga_load(fpga, axFPGABitStream_green, in main()
46 fpga_reset(fpga); in main()
/Zephyr-latest/boards/intel/niosv_g/doc/
Dindex.rst3 INTEL FPGA niosv_g
9 niosv_g board is based on Intel FPGA Design Store Nios® V/g Hello World Example Design system and t…
13 Nios® V/g Processor Intel® FPGA IP
14 JTAG UART Intel® FPGA IP
15 On-Chip Memory Intel® FPGA IP
20 Prebuilt Nios® V/g hello world example design system is available in Intel FPGA Design store.
24 - https://www.intel.com/content/www/us/en/design-example/776196/intel-arria-10-fpga-hello-world-des…
28 Create Nios® V/g processor example design system in FPGA
31 Please use Intel Quartus Programmer tool to program Nios® V/g processor based system into the FPGA …
33 In order to create the Nios® V/g processor inside the FPGA device, please download the generated .s…
/Zephyr-latest/samples/drivers/fpga/
Dindex.rst1 .. zephyr:code-sample-category:: fpga
2 :name: FPGA
5 These samples demonstrate how to use the FPGA driver API.
/Zephyr-latest/boards/intel/niosv_m/doc/
Dindex.rst3 INTEL FPGA niosv_m
9 niosv_m board is based on Intel FPGA Design Store Nios® V/m Hello World Example Design system and t…
13 Nios® V/m Processor Intel® FPGA IP
14 JTAG UART Intel® FPGA IP
15 On-Chip Memory Intel® FPGA IP
20 Prebuilt Nios® V/m hello world example design system is available in Intel FPGA Design store.
28 Create Nios® V/m processor example design system in FPGA
31 Please use Intel Quartus Programmer tool to program Nios® V/m processor based system into the FPGA …
33 In order to create the Nios® V/m processor inside the FPGA device, please download the generated .s…
/Zephyr-latest/dts/bindings/fpga/
Dlattice,ice40-fpga.yaml4 description: Lattice iCE40 FPGA SPI based driver
6 compatible: "lattice,ice40-fpga"
8 include: lattice,ice40-fpga-base.yaml
Dxlnx,fpga.yaml4 description: Zynqmp FPGA driver
6 compatible: "xlnx,fpga"
/Zephyr-latest/soc/intel/intel_niosv/niosv/
DKconfig.soc9 Intel FPGA NIOSV
18 Intel FPGA NIOSV Microcontroller Core Processor
24 Intel FPGA NIOSV General Purpose Processor
/Zephyr-latest/samples/boards/quicklogic/qomu/src/
Dmain.c10 #include <zephyr/drivers/fpga.h>
19 const struct device *fpga = device_get_binding("fpga"); in main() local
22 fpga_load(fpga, axFPGABitStream, axFPGABitStream_length); in main()
/Zephyr-latest/tests/drivers/build_all/fpga/
Dtestcase.yaml9 drivers.fpga.build:
10 tags: fpga
/Zephyr-latest/boards/shields/v2c_daplink/doc/
Dindex.rst3 ARM V2C-DAPLink for DesignStart FPGA
9 The `ARM V2C-DAPLink for DesignStart FPGA`_ shield can be used to provide
10 DAPLink debug access to the ARM DesignStart FPGA reference designs implemented
50 .. _ARM V2C-DAPLink for DesignStart FPGA:
/Zephyr-latest/drivers/reset/
DKconfig.intel_socfpga5 bool "Intel SoC FPGA Reset Controller driver"
9 Enable the Reset driver for Intel SoC FPGA device
/Zephyr-latest/soc/intel/intel_socfpga/agilex/
DKconfig.soc8 Intel SoC FPGA Agilex Series
17 Intel SoC FPGA Agilex
/Zephyr-latest/soc/intel/intel_socfpga/agilex5/
DKconfig.soc8 Intel SoC FPGA Agilex5 Series
17 Intel SoC FPGA Agilex5
/Zephyr-latest/boards/intel/socfpga/agilex5_socdk/doc/
Dindex.rst3 Intel® Agilex™ 5 SoC FPGA Development Kit
9 The Intel® Agilex™ 5 SoC FPGA Development Kit offers a complete design
11 Intel® Agilex™ 5 E-Series based FPGA designs. This kit is recommended for
20 - Intel® Agilex™ 5 E-Series FPGA, 50K-656K LEs integrated with
23 - On-board JTAG Intel FPGA Download Cable II
80 `Intel® Agilex™ 5 FPGA and SoC FPGA <https://www.intel.in/content/www/in/en/products/details/fpga/a…

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