| /Zephyr-Core-3.5.0/drivers/fpga/ |
| D | Kconfig | 1 # FPGA driver configuration options
6 menuconfig FPGA config
7 bool "Field-Programmable Gate Array (FPGA) drivers"
9 Enable support for FPGA drivers.
11 if FPGA
13 module = fpga
14 module-str = fpga
21 FPGA device drivers initialization priority
24 bool "FPGA Shell"
25 depends on SHELL && FPGA
[all …]
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| D | Kconfig.eos_s3 | 1 # FPGA EOS S3 driver configuration options
7 bool "EOS S3 fpga driver"
9 Enable EOS S3 FPGA driver.
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| D | Kconfig.zynqmp | 1 # FPGA ZYNQMP driver configuration options
7 bool "ZYNQMP fpga driver"
9 Enable ZYNQMP FPGA driver.
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| D | Kconfig.ice40 | 5 bool "Lattice iCE40 fpga driver [EXPERIMENTAL]"
10 Enable support for the Lattice iCE40 fpga driver.
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| /Zephyr-Core-3.5.0/samples/drivers/fpga/fpga_controller/ |
| D | README.rst | 1 .. zephyr:code-sample:: fpga-controller
2 :name: FPGA Controller
4 Load a bitstream into an FPGA and perform basic operations on it.
8 This module is an FPGA driver that can easily load a bitstream, reset it, check its status, enable …
9 This sample demonstrates how to use the FPGA driver API and the FPGA controller shell subsystem.
26 :zephyr-app: samples/drivers/fpga/fpga_controller
32 To build the FPGA Controller shell application, use the supplied
36 :zephyr-app: samples/drivers/fpga/fpga_controller
54 For the FPGA controller shell application, after connecting to the shell console you should see the…
68 The FPGA controller command can now be used (``fpga load <device> <address> <size in bytes>``):
[all …]
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| D | sample.yaml | 2 name: FPGA Controller sample
5 tags: FPGA
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/ |
| D | fpga.h | 21 /* Inactive is when the FPGA cannot accept the bitstream
25 /* Active is when the FPGA can accept the bitstream and
49 * @brief Read the status of FPGA.
51 * @param dev FPGA device structure.
53 * @retval 0 if the FPGA is in INACTIVE state.
54 * @retval 1 if the FPGA is in ACTIVE state.
65 * @brief Reset the FPGA.
67 * @param dev FPGA device structure.
81 * @brief Load the bitstream and program the FPGA
83 * @param dev FPGA device structure.
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/arty/doc/ |
| D | index.rst | 9 The `Digilent Arty`_ is a line of FPGA-based development boards aimed for makers
11 different Xilinx FPGA (Spartan-7, Artix-7, or Zynq-7000 series).
13 Each board is equipped with on-board JTAG for FPGA programming and debugging,
14 LEDs, switches, buttons, DDR3 RAM, and QSPI flash for storing the FPGA
24 so-called soft processor to be instantiated within the FPGA in order to run
27 ARM Cortex-M1/M3 DesignStart FPGA
31 DesignStart FPGA`_ Xilinx edition reference designs from ARM. Zephyr supports
37 For more information about the ARM Cortex-M1/M3 DesignStart FPGA, see the
40 - `Technical Resources for DesignStart FPGA`_
41 - `Technical Resources for DesignStart FPGA on Xilinx`_
[all …]
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| /Zephyr-Core-3.5.0/samples/drivers/fpga/fpga_controller/src/ |
| D | main.c | 11 #include <zephyr/drivers/fpga.h>
16 const struct device *const fpga = DEVICE_DT_GET(DT_NODELABEL(fpga0)); variable
34 if (!device_is_ready(fpga)) { in main()
35 printk("fpga device is not ready\n"); in main()
39 fpga_load(fpga, axFPGABitStream_red, in main()
42 fpga_reset(fpga); in main()
43 fpga_load(fpga, axFPGABitStream_green, in main()
46 fpga_reset(fpga); in main()
|
| /Zephyr-Core-3.5.0/boards/riscv/niosv_g/doc/ |
| D | index.rst | 3 INTEL FPGA niosv_g
9 niosv_g board is based on Intel FPGA Design Store Nios® V/g Hello World Example Design system and t…
13 Nios® V/g Processor Intel® FPGA IP
14 JTAG UART Intel® FPGA IP
15 On-Chip Memory Intel® FPGA IP
20 Prebuilt Nios® V/g hello world example design system is available in Intel FPGA Design store.
24 - https://www.intel.com/content/www/us/en/design-example/776196/intel-arria-10-fpga-hello-world-des…
28 Create Nios® V/g processor example design system in FPGA
31 Please use Intel Quartus Programmer tool to program Nios® V/g processor based system into the FPGA …
33 In order to create the Nios® V/g processor inside the FPGA device, please download the generated .s…
|
| /Zephyr-Core-3.5.0/boards/riscv/niosv_m/doc/ |
| D | index.rst | 3 INTEL FPGA niosv_m
9 niosv_m board is based on Intel FPGA Design Store Nios® V/m Hello World Example Design system and t…
13 Nios® V/m Processor Intel® FPGA IP
14 JTAG UART Intel® FPGA IP
15 On-Chip Memory Intel® FPGA IP
20 Prebuilt Nios® V/m hello world example design system is available in Intel FPGA Design store.
28 Create Nios® V/m processor example design system in FPGA
31 Please use Intel Quartus Programmer tool to program Nios® V/m processor based system into the FPGA …
33 In order to create the Nios® V/m processor inside the FPGA device, please download the generated .s…
|
| /Zephyr-Core-3.5.0/soc/arm/intel_socfpga_std/cyclonev/ |
| D | Kconfig.soc | 4 # Adding support to Cyclone V SoC FPGA
7 prompt "Intel SoC FPGA Cyclone5"
11 bool "Intel SoC FPGA Cyclone5"
|
| D | Kconfig.series | 4 # Adding configuration options for Cyclone V SoC FPGA
7 bool "Intel SoC FPGA Cyclone5 Series"
15 Support for Intel SoC FPGA Series
|
| /Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/niosv/ |
| D | Kconfig.soc | 5 prompt "FPGA NIOSV"
9 bool "Intel FPGA NIOSV Microcontroller Core Processor"
18 bool "Intel FPGA NIOSV General Purpose Processor"
|
| D | Kconfig.series | 5 bool "INTEL FPGA NIOSV"
9 Enable support for the INTEL FPGA NIOSV.
|
| /Zephyr-Core-3.5.0/samples/boards/qomu/src/ |
| D | main.c | 10 #include <zephyr/drivers/fpga.h>
19 const struct device *fpga = device_get_binding("fpga"); in main() local
22 fpga_load(fpga, axFPGABitStream, axFPGABitStream_length); in main()
|
| /Zephyr-Core-3.5.0/tests/drivers/build_all/fpga/ |
| D | testcase.yaml | 8 fpga.build:
9 tags: fpga
|
| /Zephyr-Core-3.5.0/boards/shields/v2c_daplink/doc/ |
| D | index.rst | 3 ARM V2C-DAPLink for DesignStart FPGA
9 The `ARM V2C-DAPLink for DesignStart FPGA`_ shield can be used to provide
10 DAPLink debug access to the ARM DesignStart FPGA reference designs implemented
50 .. _ARM V2C-DAPLink for DesignStart FPGA:
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| /Zephyr-Core-3.5.0/dts/bindings/fpga/ |
| D | xlnx,fpga.yaml | 4 description: Zynqmp FPGA driver
6 compatible: "xlnx,fpga"
|
| /Zephyr-Core-3.5.0/soc/arm64/intel_socfpga/agilex/ |
| D | Kconfig.soc | 5 prompt "Intel SoC FPGA Agilex"
9 bool "Intel SoC FPGA Agilex"
|
| D | Kconfig.series | 5 bool "Intel SoC FPGA Agilex Series"
10 Enable support for Intel SoC FPGA Series
|
| /Zephyr-Core-3.5.0/soc/arm64/intel_socfpga/agilex5/ |
| D | Kconfig.soc | 5 prompt "Intel SoC FPGA Agilex5"
9 bool "Intel SoC FPGA Agilex5"
|
| D | Kconfig.series | 5 bool "Intel SoC FPGA Agilex5 Series"
10 Enable support for Intel SoC FPGA Series
|
| /Zephyr-Core-3.5.0/boards/arm64/intel_socfpga_agilex5_socdk/doc/ |
| D | index.rst | 3 Intel® Agilex™ 5 SoC FPGA Development Kit
9 The Intel® Agilex™ 5 SoC FPGA Development Kit offers a complete design
11 Intel® Agilex™ 5 E-Series based FPGA designs. This kit is recommended for
20 - Intel® Agilex™ 5 E-Series FPGA, 50K-656K LEs integrated with
23 - On-board JTAG Intel FPGA Download Cable II
80 `Intel® Agilex™ 5 FPGA and SoC FPGA <https://www.intel.in/content/www/in/en/products/details/fpga/a…
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| /Zephyr-Core-3.5.0/drivers/reset/ |
| D | Kconfig.intel_socfpga | 5 bool "Intel SoC FPGA Reset Controller driver"
9 Enable the Reset driver for Intel SoC FPGA device
|
