Searched full:fe310 (Results 1 – 16 of 16) sorted by relevance
| /Zephyr-Core-3.5.0/boards/riscv/hifive1/support/ |
| D | hifive1.resc | 1 :description: This script is prepared to run Zephyr on SiFive-FE310 board.
2 :name: SiFive-FE310
4 $name?="SiFive-FE310"
8 using "platforms/cpus/sifive-fe310.repl"
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| /Zephyr-Core-3.5.0/boards/riscv/sparkfun_red_v_things_plus/doc/ |
| D | index.rst | 10 a SiFive FE310-G002 RISC-V SoC.
16 For more information about the SparkFun RED-V Things Plus and SiFive FE310-G002:
19 - `SiFive FE310-G002 Datasheet`_
20 - `SiFive FE310-G002 User Manual`_
60 .. _SiFive FE310-G002 Datasheet:
63 .. _SiFive FE310-G002 User Manual:
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| /Zephyr-Core-3.5.0/dts/bindings/pinctrl/ |
| D | sifive,pinctrl.yaml | 5 SiFive FE310 IO Function (iof) binding covers the IOF_EN/IOF_SEL registers
38 This binding gives a base representation of the SiFive FE310 pins
46 SiFive FE310 pin's configuration (pin, IO function).
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| D | quicklogic,eos-s3-pinctrl.yaml | 36 This binding gives a base representation of the SiFive FE310 pins
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| /Zephyr-Core-3.5.0/dts/bindings/watchdog/ |
| D | sifive,wdt.yaml | 4 description: SiFive FE310 Watchdog driver
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| /Zephyr-Core-3.5.0/boards/riscv/hifive1_revb/ |
| D | board.cmake | 3 board_runner_args(jlink "--device=FE310")
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| D | hifive1_revb.dts | 6 #include <sifive/riscv32-fe310.dtsi>
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| /Zephyr-Core-3.5.0/boards/riscv/sparkfun_red_v_things_plus/ |
| D | board.cmake | 3 board_runner_args(jlink "--device=FE310")
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| D | sparkfun_red_v_things_plus.dts | 7 #include <sifive/riscv32-fe310.dtsi>
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| /Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/sifive-freedom/ |
| D | soc.h | 36 * On FE310 and FU540, peripherals such as SPI, UART, I2C and PWM are clocked
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| /Zephyr-Core-3.5.0/boards/riscv/qemu_riscv32/ |
| D | qemu_riscv32_xip.dts | 9 #include <sifive/riscv32-fe310.dtsi>
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| /Zephyr-Core-3.5.0/boards/riscv/hifive1_revb/doc/ |
| D | index.rst | 10 a SiFive FE310-G002 RISC-V SoC.
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| /Zephyr-Core-3.5.0/boards/riscv/hifive1/doc/ |
| D | index.rst | 10 an FE310 RISC-V SoC.
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| /Zephyr-Core-3.5.0/dts/riscv/sifive/ |
| D | riscv32-fe310.dtsi | 10 compatible = "sifive,FE310G-0002-Z0-dev", "fe310-dev", "sifive-dev";
46 compatible = "sifive,FE310G-0002-Z0-soc", "fe310-soc",
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| /Zephyr-Core-3.5.0/boards/riscv/hifive1/ |
| D | hifive1.dts | 6 #include <sifive/riscv32-fe310.dtsi>
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| /Zephyr-Core-3.5.0/doc/releases/ |
| D | release-notes-3.1.rst | 1549 * :github:`44427` - SYS_CLOCK_HW_CYCLES_PER_SEC not correct for hifive1_revb / FE310
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