Searched full:el3 (Results 1 – 17 of 17) sorted by relevance
| /Zephyr-Core-3.5.0/dts/bindings/sip_svc/ |
| D | intel,agilex-socfpga-sip-smc.yaml | 17 The method of calling the EL3 firmware.The current driver only supports
18 communication with EL3 firmware.
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| /Zephyr-Core-3.5.0/include/zephyr/sip_svc/ |
| D | sip_svc.h | 16 * monitor firmware running at EL2/EL3.
67 * with hypervisor/secure monitor firmware running at EL2/EL3.
101 * SMC/HVC to hypervisor/secure monitor firmware running at EL2/EL3.
138 * @brief Client requests to send a SMC/HVC call to EL3/EL2
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| /Zephyr-Core-3.5.0/drivers/sip_svc/ |
| D | Kconfig | 10 ARM supervisory call driver for communicating with EL2 or EL3 firmware
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| D | sip_smc_intel_socfpga.c | 7 * supporting EL3 communication from zephyr.
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| /Zephyr-Core-3.5.0/arch/arm64/core/ |
| D | reset.c | 56 * Is considered an illegal return "[..] a return to EL2 when EL3 is in el3_get_next_el()
82 reg |= SCR_NS_BIT; /* EL2 / EL3 non-secure */ in z_arm64_el3_init()
110 * handle EL2 init in EL3, as it still needs to be done, in z_arm64_el3_init()
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| D | smccc-call.S | 31 * handled by Secure Monitor code running in EL3.
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| D | reset.S | 46 /* Reinitialize SCTLR from scratch in EL3 */
183 /* EL3 init */
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| /Zephyr-Core-3.5.0/samples/subsys/sip_svc/src/ |
| D | main.c | 7 * The access to the secure device is defined via EL3 exception level and uses
92 * mailbox command buffer size to a3 parameter ,which EL3 software will in main()
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| /Zephyr-Core-3.5.0/boards/arm64/intel_socfpga_agilex_socdk/doc/ |
| D | index.rst | 58 ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL2->EL1)
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| /Zephyr-Core-3.5.0/subsys/sip_svc/ |
| D | Kconfig | 73 Enable ARM SiP SVC service shell support to communicate with EL3/EL2
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| D | sip_svc_subsys.c | 103 * EL2/EL3 ^
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/sip_svc/ |
| D | sip_svc_proto.h | 61 * - Typical flow, synchronous request. Service expects EL3/EL2 firmware to
67 * processing in EL3/EL2.
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| /Zephyr-Core-3.5.0/boards/arm64/intel_socfpga_agilex5_socdk/doc/ |
| D | index.rst | 60 ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL1)
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| /Zephyr-Core-3.5.0/samples/subsys/sip_svc/ |
| D | README.rst | 16 * SiP SVC subsystem relies on the firmware running in EL3 layer to be in compatible
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| /Zephyr-Core-3.5.0/scripts/tests/twister/ |
| D | test_cmakecache.py | 220 ('STRING=el1;el2;el3;el4', True, ['el1', 'el2', 'el3', 'el4']),
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| /Zephyr-Core-3.5.0/drivers/interrupt_controller/ |
| D | intc_gicv3.c | 410 * 'icc_sre_el3' needs to be configured at 'EL3' in gicv3_cpuif_init()
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| /Zephyr-Core-3.5.0/doc/releases/ |
| D | release-notes-2.5.rst | 244 * Improved assembly code and errors catching in EL3 and EL1 during the
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