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Searched full:dt_size_m (Results 1 – 25 of 321) sorted by relevance

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/Zephyr-latest/boards/arm/mps3/
Dmps3_common.dtsi92 reg = <0x60000000 DT_SIZE_M(256)
93 0x70000000 DT_SIZE_M(256)
94 0x80000000 DT_SIZE_M(256)
95 0x90000000 DT_SIZE_M(256)
96 0xa0000000 DT_SIZE_M(256)
97 0xb0000000 DT_SIZE_M(256)
98 0xc0000000 DT_SIZE_M(256)
99 0xd0000000 DT_SIZE_M(256)>;
/Zephyr-latest/boards/nxp/mimxrt1170_evk/
Dmimxrt1170_evk_mimxrt1176_cm4_B.overlay23 reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(64)>;
26 size = <DT_SIZE_M(64*8)>;
48 reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>;
52 reg = <0x00723000 DT_SIZE_M(7)>;
56 reg = <0x00E23000 (DT_SIZE_M(50) - DT_SIZE_K(140))>;
Dmimxrt1170_evk_mimxrt1176_cm7_B.overlay26 reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(64)>;
29 size = <DT_SIZE_M(64*8)>;
51 reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>;
55 reg = <0x00723000 DT_SIZE_M(7)>;
59 reg = <0x00E23000 (DT_SIZE_M(50) - DT_SIZE_K(140))>;
/Zephyr-latest/boards/nxp/mimxrt1050_evk/
Dmimxrt1050_evk_mimxrt1052_hyperflash.dts28 reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>;
31 size = <DT_SIZE_M(64*8)>;
60 reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(512))>;
64 reg = <0x003C0000 DT_SIZE_M(3)>;
68 reg = <0x006C0000 (DT_SIZE_M(58) - DT_SIZE_K(768))>;
Dmimxrt1050_evk_mimxrt1052_qspi.dts22 reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
45 reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>;
49 reg = <0x00322000 DT_SIZE_M(3)>;
53 reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>;
/Zephyr-latest/boards/nxp/mimxrt1060_evk/
Dmimxrt1060_evk_mimxrt1062_hyperflash.dts26 reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>;
29 size = <DT_SIZE_M(64*8)>;
58 reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(512))>;
62 reg = <0x003C0000 DT_SIZE_M(3)>;
66 reg = <0x006C0000 (DT_SIZE_M(58) - DT_SIZE_K(768))>;
Dmimxrt1060_evk_mimxrt1062_qspi.dts24 reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
48 reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>;
52 reg = <0x00322000 DT_SIZE_M(3)>;
56 reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>;
/Zephyr-latest/boards/nxp/frdm_mcxn947/
Dfrdm_mcxn947_mcxn947_cpu0_qspi.dts33 reg = <0x00000000 DT_SIZE_M(3)>;
37 reg = <0x00300000 DT_SIZE_M(3)>;
41 reg = <0x00600000 DT_SIZE_M(2)>;
/Zephyr-latest/dts/xtensa/espressif/esp32s2/
Desp32s2_fn4r2.dtsi11 reg = <0x0 DT_SIZE_M(4)>;
16 reg = <0x3f500000 DT_SIZE_M(2)>;
Desp32s2_mini_n4r2.dtsi11 reg = <0x0 DT_SIZE_M(4)>;
17 reg = <0x3f500000 DT_SIZE_M(2)>;
Desp32s2_solo_n4r2.dtsi11 reg = <0x0 DT_SIZE_M(4)>;
17 reg = <0x3f500000 DT_SIZE_M(2)>;
Desp32s2_wrover_n16r2.dtsi11 reg = <0x0 DT_SIZE_M(16)>;
17 reg = <0x3f500000 DT_SIZE_M(2)>;
Desp32s2_wrover_n4r2.dtsi11 reg = <0x0 DT_SIZE_M(4)>;
17 reg = <0x3f500000 DT_SIZE_M(2)>;
Desp32s2_wrover_n8r2.dtsi11 reg = <0x0 DT_SIZE_M(8)>;
17 reg = <0x3f500000 DT_SIZE_M(2)>;
/Zephyr-latest/dts/xtensa/espressif/esp32s3/
Desp32s3_mini_n4r2.dtsi11 reg = <0x0 DT_SIZE_M(4)>;
16 reg = <0x3c000000 DT_SIZE_M(2)>;
Desp32s3_pico_n8r2.dtsi11 reg = <0x0 DT_SIZE_M(8)>;
16 reg = <0x3c000000 DT_SIZE_M(2)>;
Desp32s3_pico_n8r8.dtsi11 reg = <0x0 DT_SIZE_M(8)>;
16 reg = <0x3c000000 DT_SIZE_M(8)>;
Desp32s3_wroom_n16r2.dtsi11 reg = <0x0 DT_SIZE_M(16)>;
16 reg = <0x3c000000 DT_SIZE_M(2)>;
Desp32s3_wroom_n16r8.dtsi11 reg = <0x0 DT_SIZE_M(16)>;
16 reg = <0x3c000000 DT_SIZE_M(8)>;
Desp32s3_wroom_n4r2.dtsi11 reg = <0x0 DT_SIZE_M(4)>;
16 reg = <0x3c000000 DT_SIZE_M(2)>;
Desp32s3_wroom_n4r8.dtsi11 reg = <0x0 DT_SIZE_M(4)>;
16 reg = <0x3c000000 DT_SIZE_M(8)>;
Desp32s3_wroom_n8r2.dtsi11 reg = <0x0 DT_SIZE_M(8)>;
16 reg = <0x3c000000 DT_SIZE_M(2)>;
Desp32s3_wroom_n8r8.dtsi11 reg = <0x0 DT_SIZE_M(8)>;
16 reg = <0x3c000000 DT_SIZE_M(8)>;
/Zephyr-latest/boards/beagle/beaglebone_ai64/
Dbeaglebone_ai64_j721e_main_r5f0_0.dts32 reg = <0xa2000000 DT_SIZE_M(1)>;
37 reg = <0xa2100000 DT_SIZE_M(1)>;
43 reg = <0xa2200000 DT_SIZE_M(14)>;
/Zephyr-latest/dts/xtensa/espressif/esp32/
Desp32_pico_v3_02.dtsi17 reg = <0x0 DT_SIZE_M(8)>;
22 reg = <0x3f800000 DT_SIZE_M(2)>;

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