Searched full:divr (Results 1 – 4 of 4) sorted by relevance
40 PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */ in fu740_clock_init()54 PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */ in fu740_clock_init()
64 PLLx DIVR division factor
70 PLLx DIVR division factor
718 /* FRACN disable DIVP,DIVQ,DIVR enable*/ in set_up_plls()