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/Zephyr-Core-3.6.0/soc/riscv/sifive_freedom/u700/
Dclock.c40 PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */ in fu740_clock_init()
54 PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */ in fu740_clock_init()
/Zephyr-Core-3.6.0/dts/bindings/clock/
Dst,stm32wba-pll-clock.yaml64 PLLx DIVR division factor
Dst,stm32u5-pll-clock.yaml70 PLLx DIVR division factor
/Zephyr-Core-3.6.0/drivers/clock_control/
Dclock_stm32_ll_h7.c718 /* FRACN disable DIVP,DIVQ,DIVR enable*/ in set_up_plls()