| /Zephyr-latest/tests/drivers/spi/spi_controller_peripheral/ |
| D | Kconfig | 9 0: CPOL 0 (Active high), CPHA 0 (leading)
10 1: CPOL 0 (Active high), CPHA 1 (trailing)
11 2: CPOL 1 (Active low), CPHA 0 (leading)
12 3: CPOL 1 (Active low), CPHA 1 (trailing)
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| D | README.txt | 3 In each test, both instances get identical configuration (CPOL, CPHA, bitrate, etc.).
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| /Zephyr-latest/dts/bindings/wifi/ |
| D | nordic,nrf70-qspi.yaml | 37 The driver using this property must also use `cpol`.
39 qspi-cpol:
42 Set to indicate that the clock leading edge is falling (CPOL=1).
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| /Zephyr-latest/boards/shields/x_nucleo_wb05kn1/ |
| D | x_nucleo_wb05kn1_spi.overlay | 21 spi-cpol; /* CPOL=1 */
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| /Zephyr-latest/dts/bindings/sdhc/ |
| D | zephyr,sdhc-spi-slot.yaml | 16 spi-clock-mode-cpol:
26 on the clock's polarity. When mode-cpol is set and this option as well,
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| /Zephyr-latest/dts/bindings/mtd/ |
| D | nordic,qspi-nor.yaml | 86 For this driver using this property requires also using cpol.
88 cpol:
91 Set to indicate clock leading edge is falling (CPOL=1).
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| /Zephyr-latest/dts/bindings/mspi/ |
| D | mspi-device.yaml | 71 MSPI_CPP_MODE_0: CPOL=0, CPHA=0
72 MSPI_CPP_MODE_1: CPOL=0, CPHA=1
73 MSPI_CPP_MODE_2: CPOL=1, CPHA=0
74 MSPI_CPP_MODE_3: CPOL=1, CPHA=1
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| /Zephyr-latest/samples/subsys/fs/fs_sample/boards/ |
| D | nucleo_f429zi.overlay | 18 spi-clock-mode-cpol;
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| /Zephyr-latest/drivers/spi/ |
| D | spi_sedi.c | 42 uint32_t word_size, cpol, cpha, loopback; in spi_sedi_configure() local
52 /* CPOL and CPHA */ in spi_sedi_configure()
53 cpol = SPI_MODE_GET(config->operation) & SPI_MODE_CPOL; in spi_sedi_configure()
56 if ((cpol == 0) && (cpha == 0)) { in spi_sedi_configure()
59 } else if ((cpol == 0) && (cpha == 1U)) { in spi_sedi_configure()
62 } else if ((cpol == 1) && (cpha == 0U)) { in spi_sedi_configure()
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| D | spi_xec_qmspi.c | 93 * SPI signalling mode: CPOL and CPHA
94 * CPOL = 0 is clock idles low, 1 is clock idle high
100 * Mode CPOL CPHA
105 * MEC1501 has three controls, CPOL, CPHA for output and CPHA for input.
107 * Mode 0: CPOL=0 CHPA=0 (CHPA_MISO=0 and CHPA_MOSI=0)
108 * Mode 3: CPOL=1 CHPA=1 (CHPA_MISO=1 and CHPA_MOSI=1)
111 * Mode 0: CPOL=0 CHPA=0 (CHPA_MISO=1 and CHPA_MOSI=0)
112 * Mode 3: CPOL=1 CHPA=1 (CHPA_MISO=0 and CHPA_MOSI=1)
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| D | spi_numaker.c | 42 * CPOL/CPHA = 0/0 --> SPI_MODE_0
43 * CPOL/CPHA = 0/1 --> SPI_MODE_1
44 * CPOL/CPHA = 1/0 --> SPI_MODE_2
45 * CPOL/CPHA = 1/1 --> SPI_MODE_3
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| D | spi_xec_qmspi_ldma.c | 216 * SPI signalling mode: CPOL and CPHA
217 * CPOL = 0 is clock idles low, 1 is clock idle high
223 * Mode CPOL CPHA
228 * QMSPI has three controls, CPOL, CPHA for output and CPHA for input.
230 * Mode 0: CPOL=0 CHPA=0 (CHPA_MISO=0 and CHPA_MOSI=0)
231 * Mode 3: CPOL=1 CHPA=1 (CHPA_MISO=1 and CHPA_MOSI=1)
234 * Mode 0: CPOL=0 CHPA=0 (CHPA_MISO=1 and CHPA_MOSI=0)
235 * Mode 3: CPOL=1 CHPA=1 (CHPA_MISO=0 and CHPA_MOSI=1)
244 0x03u, /* CPOL=1, CPHA_MOSI=1, CPHA_MISO=0 */
246 0x07u, /* CPOL=1, CPHA_MOSI=1, CPHA_MISO=1 */
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| D | spi_rpi_pico_pio.c | 205 uint32_t cpol = 0; in spi_pico_pio_configure() local
260 cpol = 1; in spi_pico_pio_configure()
272 if ((cpol != 0) || (cpha != 0)) { in spi_pico_pio_configure()
358 if ((cpol == 0) && (cpha == 0)) { in spi_pico_pio_configure()
363 } else if ((cpol == 1) && (cpha == 1)) { in spi_pico_pio_configure()
369 LOG_ERR("Not supported: cpol=%d, cpha=%d\n", cpol, cpha); in spi_pico_pio_configure()
405 pio_sm_set_pins_with_mask(data->pio, data->pio_sm, (cpol << clk->pin), in spi_pico_pio_configure()
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| D | spi_xmc4xxx.c | 196 bool CPOL = SPI_MODE_GET(settings) & SPI_MODE_CPOL; in spi_xmc4xxx_configure() local
236 if (!CPOL && !CPHA) { in spi_xmc4xxx_configure()
238 } else if (!CPOL && CPHA) { in spi_xmc4xxx_configure()
240 } else if (CPOL && !CPHA) { in spi_xmc4xxx_configure()
242 } else if (CPOL && CPHA) { in spi_xmc4xxx_configure()
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| D | spi_npcx_spip.c | 107 * Set CPOL and CPHA. in spi_npcx_spip_configure()
108 * The following is how to map npcx spip control register to CPOL and CPHA in spi_npcx_spip_configure()
109 * CPOL CPHA | SCIDL SCM in spi_npcx_spip_configure()
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| D | spi_grlib_spimctrl.c | 79 LOG_ERR("Only supports CPOL=CPHA=0"); in spi_config()
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| D | spi_litex.c | 94 LOG_ERR("Only supports CPOL=CPHA=0"); in spi_config()
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| D | spi_litex_litespi.c | 103 LOG_ERR("Only supports CPOL=CPHA=0"); in spi_config()
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| D | spi_sifive.c | 55 /* If CPOL is set, then SCK idles at logical 1 */ in spi_config()
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| D | spi_max32.c | 109 int cpol = (SPI_MODE_GET(config->operation) & SPI_MODE_CPOL) ? 1 : 0; in spi_configure() local
112 if (cpol && cpha) { in spi_configure()
116 } else if (cpol) { in spi_configure()
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| /Zephyr-latest/soc/microchip/mec/ |
| D | Kconfig | 200 input/output data phases. Bits[0:2] are CPOL:CPHA_MOSI:CPHA_MISO. Refer
203 Setting this field to 0 selects mode 0, CPOL=0, CPHA_MOSI=0, CPHA_MISO=0
204 Setting this filed to 7 selects mode 3, CPOL=1, CPHA_MOSI=1, CPHA_MISO=1
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| /Zephyr-latest/dts/bindings/mipi-dbi/ |
| D | mipi-dbi-spi-device.yaml | 21 mipi-cpol:
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| /Zephyr-latest/dts/bindings/spi/ |
| D | spi-device.yaml | 43 spi-cpol:
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| /Zephyr-latest/boards/segger/ip_k66f/ |
| D | ip_k66f.dts | 142 spi-cpol;
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| /Zephyr-latest/drivers/flash/ |
| D | nrf_qspi_nor.c | 146 /* 0 for MODE0 (CPOL=0, CPHA=0), 1 for MODE3 (CPOL=1, CPHA=1). */
147 #define INST_0_SPI_MODE DT_INST_PROP(0, cpol)
148 BUILD_ASSERT(DT_INST_PROP(0, cpol) == DT_INST_PROP(0, cpha),
149 "Invalid combination of \"cpol\" and \"cpha\" properties.");
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