Searched full:clkdiv (Results 1 – 11 of 11) sorted by relevance
| /Zephyr-latest/drivers/led_strip/ |
| D | ws2812_rpi_pico_pio.c | 43 const float clkdiv = in ws2812_led_strip_sm_init() local
60 sm_config_set_clkdiv(&sm_config, clkdiv); in ws2812_led_strip_sm_init()
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| /Zephyr-latest/drivers/timer/ |
| D | gecko_burtc_timer.c | 208 init.clkDiv = 1; in burtc_init()
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| /Zephyr-latest/dts/bindings/memory-controllers/ |
| D | st,stm32-fmc-nor-psram.yaml | 154 * CLKDIV - Clock divide ratio (for FMC_CLK signal).
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| /Zephyr-latest/soc/microchip/mec/common/reg/ |
| D | mec_timers.h | 264 volatile uint32_t CLKDIV; member
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| /Zephyr-latest/drivers/spi/ |
| D | spi_opentitan.c | 109 * Applied divider (divides f_in / 2) is CLKDIV register (16 bit) + 1. in spi_config()
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| /Zephyr-latest/drivers/adc/ |
| D | adc_max32.c | 249 .clkdiv = config->clock_divider, in adc_max32_init()
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_mchp_xec.c | 756 static void xec_clock_control_core_clock_divider_set(uint8_t clkdiv) in xec_clock_control_core_clock_divider_set() argument
764 pcr->PROC_CLK_CTRL = (uint32_t)clkdiv; in xec_clock_control_core_clock_divider_set()
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| /Zephyr-latest/drivers/espi/ |
| D | espi_saf_mchp_xec_v2.c | 466 LOG_ERR("%s SAF CLKDIV CS0 bad freq MHz %u", in saf_flash_freq_cfg()
480 LOG_ERR("%s SAF CLKDIV CS1 bad freq MHz %u", in saf_flash_freq_cfg()
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| /Zephyr-latest/drivers/dai/intel/dmic/ |
| D | dmic_nhlt.c | 577 LOG_DBG(" clkdiv=%d, skew=%d, clk_edge=%d", bf5, bf1, bf2); in print_pdm_ctrl()
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| /Zephyr-latest/drivers/sdhc/ |
| D | sdhc_esp32.c | 824 int card_div = 0; /* 1/2 of card clock divider (sdio_hw->clkdiv) */ in sdmmc_host_set_card_clk()
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| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | numaker_m46x_clock.h | 580 * APBCLK(31:29)|CLKSEL(28:26)|CLKSEL_Msk(25:22)|CLKSEL_Pos(21:17)|CLKDIV(16:14)|
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