Searched full:cclk (Results 1 – 4 of 4) sorted by relevance
| /Zephyr-latest/soc/telink/tlsr/tlsr951x/ |
| D | soc.c | 16 /* List of supported CCLK frequencies */
24 /* Define 48 MHz and 96 MHz CCLK clock options (not present in HAL) */
76 unsigned int cclk = DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency); in soc_early_init_hook() local
82 /* clocks init: CCLK, HCLK, PCLK */ in soc_early_init_hook()
83 switch (cclk) { in soc_early_init_hook()
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| /Zephyr-latest/dts/bindings/spi/ |
| D | xlnx,xps-spi-2.00.a.yaml | 50 disengaged and allow the SPI core to control the CCLK line properly.
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| /Zephyr-latest/drivers/spi/ |
| D | spi_xlnx_axi_quadspi.c | 514 * is passed to the output CCLK pin from the SPI core. in xlnx_quadspi_startup_block_workaround()
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| /Zephyr-latest/drivers/modem/ |
| D | hl7800.c | 1184 ret = send_at_cmd(NULL, "AT+CCLK?", MDM_CMD_SEND_TIMEOUT, 0, false); in mdm_hl7800_get_local_time()
3569 /* Handler: +CCLK: "yy/MM/dd,hh:mm:ss±zz" */
4618 CMD_HANDLER("+CCLK: ", rtc_query), in hl7800_rx()
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