| /Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/common/include/ |
| D | intel_adsp_hda.h | 21 * usage. The only requirement is that you define the base
34 /* Calculate base address of the stream registers */
35 #define HDA_ADDR(base, regblock_size, stream) ((base) + (stream)*(regblock_size)) argument
38 #define DGCS(base, regblock_size, stream) \ argument
39 ((volatile uint32_t *)HDA_ADDR(base, regblock_size, stream))
55 /* Gateway Buffer Base Address */
56 #define DGBBA(base, regblock_size, stream) \ argument
57 ((volatile uint32_t *)(HDA_ADDR(base, regblock_size, stream) + 0x04))
60 #define DGBS(base, regblock_size, stream) \ argument
61 ((volatile uint32_t *)(HDA_ADDR(base, regblock_size, stream) + 0x08))
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| /Zephyr-Core-3.6.0/drivers/spi/ |
| D | spi_andes_atcspi200.h | 29 #define SPI_TFMAT(base) (base + REG_TFMAT) argument
30 #define SPI_TCTRL(base) (base + REG_TCTRL) argument
31 #define SPI_CMD(base) (base + REG_CMD) argument
32 #define SPI_DATA(base) (base + REG_DATA) argument
33 #define SPI_CTRL(base) (base + REG_CTRL) argument
34 #define SPI_STAT(base) (base + REG_STAT) argument
35 #define SPI_INTEN(base) (base + REG_INTEN) argument
36 #define SPI_INTST(base) (base + REG_INTST) argument
37 #define SPI_TIMIN(base) (base + REG_TIMIN) argument
38 #define SPI_CONFIG(base) (base + REG_CONFIG) argument
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| /Zephyr-Core-3.6.0/drivers/interrupt_controller/ |
| D | intc_gic_common_priv.h | 10 /* Offsets from GICD base or GICR(n) SGI_base */
25 #define IGROUPR(base, n) (base + GIC_DIST_IGROUPR + (n) * 4) argument
26 #define ISENABLER(base, n) (base + GIC_DIST_ISENABLER + (n) * 4) argument
27 #define ICENABLER(base, n) (base + GIC_DIST_ICENABLER + (n) * 4) argument
28 #define ISPENDR(base, n) (base + GIC_DIST_ISPENDR + (n) * 4) argument
29 #define ICPENDR(base, n) (base + GIC_DIST_ICPENDR + (n) * 4) argument
30 #define IPRIORITYR(base, n) (base + GIC_DIST_IPRIORITYR + n) argument
31 #define ITARGETSR(base, n) (base + GIC_DIST_ITARGETSR + (n) * 4) argument
32 #define ICFGR(base, n) (base + GIC_DIST_ICFGR + (n) * 4) argument
33 #define IGROUPMODR(base, n) (base + GIC_DIST_IGROUPMODR + (n) * 4) argument
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| /Zephyr-Core-3.6.0/drivers/flash/ |
| D | flash_andes_qspi.h | 30 #define QSPI_TFMAT(base) (base + 0x10) argument
31 #define QSPI_TCTRL(base) (base + 0x20) argument
32 #define QSPI_CMD(base) (base + 0x24) argument
33 #define QSPI_ADDR(base) (base + 0x28) argument
34 #define QSPI_DATA(base) (base + 0x2c) argument
35 #define QSPI_CTRL(base) (base + 0x30) argument
36 #define QSPI_STAT(base) (base + 0x34) argument
37 #define QSPI_INTEN(base) (base + 0x38) argument
38 #define QSPI_INTST(base) (base + 0x3c) argument
39 #define QSPI_TIMIN(base) (base + 0x40) argument
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| /Zephyr-Core-3.6.0/drivers/watchdog/ |
| D | wdt_dw.h | 303 * @param base Device base address.
305 static inline void dw_wdt_enable(const uint32_t base) in dw_wdt_enable() argument
307 uint32_t control = sys_read32(base + WDT_CR); in dw_wdt_enable()
310 sys_write32(control, base + WDT_CR); in dw_wdt_enable()
319 * @param base Device base address.
325 static inline void dw_wdt_response_mode_set(const uint32_t base, const bool mode) in dw_wdt_response_mode_set() argument
327 uint32_t control = sys_read32(base + WDT_CR); in dw_wdt_response_mode_set()
334 sys_write32(control, base + WDT_CR); in dw_wdt_response_mode_set()
340 * @param base Device base address.
343 static inline void dw_wdt_reset_pulse_length_set(const uint32_t base, const uint32_t pclk_cycles) in dw_wdt_reset_pulse_length_set() argument
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| D | wdt_intel_adsp.h | 86 * @param base Device base address.
89 static inline void intel_adsp_wdt_pause(uint32_t base, const uint32_t core) in intel_adsp_wdt_pause() argument
91 const uint32_t reg_addr = base + DSPCxWDTCS + DSPBRx_OFFSET(core); in intel_adsp_wdt_pause()
105 * @param base Device base address.
108 static inline void intel_adsp_wdt_resume(uint32_t base, const uint32_t core) in intel_adsp_wdt_resume() argument
110 const uint32_t reg_addr = base + DSPCxWDTCS + DSPBRx_OFFSET(core); in intel_adsp_wdt_resume()
124 * @param base Device base address.
127 static inline void intel_adsp_wdt_reset_set(uint32_t base, const uint32_t core, const bool enable) in intel_adsp_wdt_reset_set() argument
129 sys_write32(enable ? DSPCxWDTCS_STORE : 0, base + DSPCxWDTCS + DSPBRx_OFFSET(core)); in intel_adsp_wdt_reset_set()
144 * Returns the base address of the watchdog IP
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| /Zephyr-Core-3.6.0/drivers/counter/ |
| D | counter_imx_epit.c | 18 EPIT_Type *base; member
35 EPIT_Type *base = get_epit_config(dev)->base; in imx_epit_isr() local
38 EPIT_ClearStatusFlag(base); in imx_epit_isr()
49 EPIT_Type *base = config->base; in imx_epit_init() local
59 config->info.freq = get_epit_clock_freq(base)/(config->prescaler + 1U); in imx_epit_init()
61 EPIT_Init(base, &epit_config); in imx_epit_init()
66 EPIT_Type *base = get_epit_config(dev)->base; in imx_epit_start() local
69 EPIT_SetClockSource(base, epitClockSourcePeriph); in imx_epit_start()
72 EPIT_SetPrescaler(base, get_epit_config(dev)->prescaler); in imx_epit_start()
75 EPIT_Enable(base); in imx_epit_start()
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| D | counter_mcux_snvs.c | 30 SNVS_Type *base; member
64 tmp = (config->base->HPRTCMR << 17U); in mcux_snvs_get_value()
65 tmp |= (config->base->HPRTCLR >> 15U); in mcux_snvs_get_value()
100 config->base->HPCR &= ~SNVS_HPCR_HPTA_EN_MASK; in mcux_snvs_set_alarm()
101 while ((config->base->HPCR & SNVS_HPCR_HPTA_EN_MASK) != 0U) { in mcux_snvs_set_alarm()
105 config->base->HPTAMR = (uint32_t)(ticks >> 17U); in mcux_snvs_set_alarm()
106 config->base->HPTALR = (uint32_t)(ticks << 15U); in mcux_snvs_set_alarm()
109 config->base->HPCR |= SNVS_HPCR_HPTA_EN_MASK; in mcux_snvs_set_alarm()
119 config->base->LPCR &= ~SNVS_LPCR_LPTA_EN_MASK; in mcux_snvs_set_alarm()
120 while ((config->base->LPCR & SNVS_LPCR_LPTA_EN_MASK) != 0U) { in mcux_snvs_set_alarm()
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| /Zephyr-Core-3.6.0/include/zephyr/net/ |
| D | mdio.h | 102 /* BASE-T1 registers */
103 /** BASE-T1 Auto-negotiation control */
105 /** BASE-T1 Auto-negotiation status */
107 /** BASE-T1 Auto-negotiation advertisement register [15:0] */
109 /** BASE-T1 Auto-negotiation advertisement register [31:16] */
111 /** BASE-T1 Auto-negotiation advertisement register [47:32] */
113 /* BASE-T1 PMA/PMD control register */
116 /* BASE-T1 Auto-negotiation Control register */
122 /* BASE-T1 Auto-negotiation Status register */
134 /* BASE-T1 Auto-negotiation Advertisement register [15:0] */
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| /Zephyr-Core-3.6.0/drivers/gpio/ |
| D | gpio_stellaris.c | 23 uint32_t base; member
34 #define GPIO_REG_ADDR(base, offset) (base + offset) argument
36 #define GPIO_RW_ADDR(base, offset, p) \ argument
37 (GPIO_REG_ADDR(base, offset) | (1 << (p + 2)))
39 #define GPIO_RW_MASK_ADDR(base, offset, mask) \ argument
40 (GPIO_REG_ADDR(base, offset) | (mask << 2))
58 uint32_t base = cfg->base; in gpio_stellaris_isr() local
59 uint32_t int_stat = sys_read32(GPIO_REG_ADDR(base, GPIO_MIS_OFFSET)); in gpio_stellaris_isr()
63 sys_write32(int_stat, GPIO_REG_ADDR(base, GPIO_ICR_OFFSET)); in gpio_stellaris_isr()
70 uint32_t base = cfg->base; in gpio_stellaris_configure() local
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| D | gpio_bcm2711.c | 17 #define GPFSEL(base, n) (base + 0x00 + 0x04 * n) argument
18 #define GPSET(base, n) (base + 0x1C + 0x04 * n) argument
19 #define GPCLR(base, n) (base + 0x28 + 0x04 * n) argument
20 #define GPLEV(base, n) (base + 0x34 + 0x04 * n) argument
21 #define GPEDS(base, n) (base + 0x40 + 0x04 * n) argument
22 #define GPREN(base, n) (base + 0x4C + 0x04 * n) argument
23 #define GPFEN(base, n) (base + 0x58 + 0x04 * n) argument
24 #define GPHEN(base, n) (base + 0x64 + 0x04 * n) argument
25 #define GPLEN(base, n) (base + 0x70 + 0x04 * n) argument
26 #define GPAREN(base, n) (base + 0x7C + 0x04 * n) argument
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| D | gpio_imx.c | 24 GPIO_Type *base; member
40 GPIO_Type *base = config->base; in imx_gpio_configure() local
91 GPIO_SetPinIntMode(base, pin, false); in imx_gpio_configure()
92 GPIO_SetIntEdgeSelect(base, pin, false); in imx_gpio_configure()
97 GPIO_WritePinOutput(base, pin, gpioPinClear); in imx_gpio_configure()
99 GPIO_WritePinOutput(base, pin, gpioPinSet); in imx_gpio_configure()
103 WRITE_BIT(base->GDIR, pin, 1U); in imx_gpio_configure()
106 WRITE_BIT(base->GDIR, pin, 0U); in imx_gpio_configure()
115 GPIO_Type *base = config->base; in imx_gpio_port_get_raw() local
117 *value = GPIO_ReadPortInput(base); in imx_gpio_port_get_raw()
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| /Zephyr-Core-3.6.0/drivers/ipm/ |
| D | ipm_imx.c | 24 #define MU(config) ((MU_Type *)config->base)
33 MU_Type *base; member
48 * @param base Register base address for the module.
53 static inline bool MU_IsRxFull(MU_Type *base, uint32_t index) in MU_IsRxFull() argument
57 return (bool)(MU_GetStatusFlags(base) & kMU_Rx0FullFlag); in MU_IsRxFull()
59 return (bool)(MU_GetStatusFlags(base) & kMU_Rx1FullFlag); in MU_IsRxFull()
61 return (bool)(MU_GetStatusFlags(base) & kMU_Rx2FullFlag); in MU_IsRxFull()
63 return (bool)(MU_GetStatusFlags(base) & kMU_Rx3FullFlag); in MU_IsRxFull()
76 * @param base Register base address for the module.
81 static inline bool MU_IsTxEmpty(MU_Type *base, uint32_t index) in MU_IsTxEmpty() argument
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| /Zephyr-Core-3.6.0/drivers/serial/ |
| D | uart_rzt2m.h | 14 #define RDR(base) ((volatile uint32_t *)(base)) argument
15 #define TDR(base) ((volatile uint32_t *)(base + 0x04)) argument
16 #define CCR0(base) ((volatile uint32_t *)(base + 0x08)) argument
17 #define CCR1(base) ((volatile uint32_t *)(base + 0x0c)) argument
18 #define CCR2(base) ((volatile uint32_t *)(base + 0x10)) argument
19 #define CCR3(base) ((volatile uint32_t *)(base + 0x14)) argument
20 #define CCR4(base) ((volatile uint32_t *)(base + 0x18)) argument
21 #define FCR(base) ((volatile uint32_t *)(base + 0x24)) argument
22 #define CSR(base) ((volatile uint32_t *)(base + 0x48)) argument
23 #define FRSR(base) ((volatile uint32_t *)(base + 0x50)) argument
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| D | uart_rzt2m.c | 23 mm_reg_t base; member
48 if (FRSR_R(*FRSR(config->base)) == 0) { in rzt2m_poll_in()
52 *c = *RDR(config->base) & RDR_MASK_RDAT; in rzt2m_poll_in()
53 *CFCLR(config->base) |= CFCLR_MASK_RDRFC; in rzt2m_poll_in()
55 if (FRSR_R(*FRSR(config->base)) == 0) { in rzt2m_poll_in()
56 *FFCLR(config->base) |= FFCLR_MASK_DRC; in rzt2m_poll_in()
74 int fifo_count = FTSR_T(*FTSR(config->base)); in rzt2m_poll_out()
77 fifo_count = FTSR_T(*FTSR(config->base)); in rzt2m_poll_out()
80 *TDR(config->base) = c; in rzt2m_poll_out()
83 *CFCLR(config->base) |= CFCLR_MASK_TDREC; in rzt2m_poll_out()
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| D | leuart_gecko.c | 24 ((const struct leuart_gecko_config * const)(dev)->config)->base)
27 LEUART_TypeDef *base; member
52 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_poll_in() local
53 uint32_t flags = LEUART_StatusGet(base); in leuart_gecko_poll_in()
56 *c = LEUART_Rx(base); in leuart_gecko_poll_in()
65 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_poll_out() local
70 LEUART_Tx(base, c); in leuart_gecko_poll_out()
75 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_err_check() local
76 uint32_t flags = LEUART_IntGet(base); in leuart_gecko_err_check()
91 LEUART_IntClear(base, LEUART_IF_RXOF | in leuart_gecko_err_check()
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| /Zephyr-Core-3.6.0/drivers/pcie/host/ |
| D | msi.c | 15 uint32_t base; in pcie_msi_base() local
21 base = pcie_get_cap(bdf, PCI_CAP_ID_MSI); in pcie_msi_base()
28 base = base_msix; in pcie_msi_base()
36 return base; in pcie_msi_base()
71 uint32_t base) in get_msix_table_size() argument
75 mcr = pcie_conf_read(bdf, base + PCIE_MSIX_MCR); in get_msix_table_size()
81 uint32_t base, in map_msix_table_entries() argument
91 table_offset = pcie_conf_read(bdf, base + PCIE_MSIX_TR); in map_msix_table_entries()
129 uint32_t base) in get_msi_mmc() argument
133 mcr = pcie_conf_read(bdf, base + PCIE_MSI_MCR); in get_msi_mmc()
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| /Zephyr-Core-3.6.0/tests/bluetooth/audio/bap_base/src/ |
| D | main.c | 59 /* Modify the CC length to generate an invalid BASE for invalid BASE tests */ in bap_base_test_suite_fixture_init()
103 const struct bt_bap_base *base = bt_bap_base_get_base_from_ad(&fixture->valid_base_ad); in ZTEST_F() local
105 zassert_not_null(base); in ZTEST_F()
110 const struct bt_bap_base *base = bt_bap_base_get_base_from_ad(&fixture->invalid_base_ad); in ZTEST_F() local
112 zassert_is_null(base); in ZTEST_F()
117 const struct bt_bap_base *base = bt_bap_base_get_base_from_ad(NULL); in ZTEST_F() local
119 zassert_is_null(base); in ZTEST_F()
124 const struct bt_bap_base *base; in ZTEST_F() local
128 base = bt_bap_base_get_base_from_ad(&fixture->valid_base_ad); in ZTEST_F()
130 zassert_is_null(base); in ZTEST_F()
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| /Zephyr-Core-3.6.0/drivers/usb/device/ |
| D | usb_dc_dw.c | 63 #define USB_DW_EP_FIFO(base, idx) \ argument
64 (*(uint32_t *)(POINTER_TO_UINT(base) + 0x1000 * (idx + 1)))
67 struct usb_dwc2_reg *const base; member
71 int (*pwr_on_func)(struct usb_dwc2_reg *const base);
169 .base = (struct usb_dwc2_reg *)DT_INST_REG_ADDR(n), \
185 struct usb_dwc2_reg *const base = usb_dw_cfg.base; in usb_dw_reg_dump() local
189 "0x%x", base->gotgctl, base->gotgint, base->gahbcfg); in usb_dw_reg_dump()
191 base->gusbcfg, base->gintsts, base->gintmsk); in usb_dw_reg_dump()
193 base->dcfg, base->dctl, base->dsts); in usb_dw_reg_dump()
195 base->diepmsk, base->doepmsk, base->daint); in usb_dw_reg_dump()
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| /Zephyr-Core-3.6.0/drivers/memc/ |
| D | memc_nxp_flexram.c | 89 static FLEXRAM_Type *const base = (FLEXRAM_Type *) DT_REG_ADDR(FLEXRAM_DT_NODE);
110 if (base->INT_STATUS & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK) { in nxp_flexram_isr()
111 base->INT_STATUS |= FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK; in nxp_flexram_isr()
114 if (base->INT_STATUS & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK) { in nxp_flexram_isr()
115 base->INT_STATUS |= FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK; in nxp_flexram_isr()
118 if (base->INT_STATUS & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK) { in nxp_flexram_isr()
119 base->INT_STATUS |= FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK; in nxp_flexram_isr()
125 if (base->INT_STATUS & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK) { in nxp_flexram_isr()
126 base->INT_STATUS |= FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK; in nxp_flexram_isr()
129 if (base->INT_STATUS & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK) { in nxp_flexram_isr()
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| /Zephyr-Core-3.6.0/subsys/pm/ |
| D | device_runtime.c | 55 if (!atomic_test_bit(&pm->base.flags, PM_DEVICE_FLAG_RUNTIME_ENABLED)) { in runtime_suspend()
68 if (pm->base.usage == 0U) { in runtime_suspend()
74 pm->base.usage--; in runtime_suspend()
75 if (pm->base.usage > 0U) { in runtime_suspend()
81 pm->base.state = PM_DEVICE_STATE_SUSPENDING; in runtime_suspend()
85 ret = pm->base.action_cb(pm->dev, PM_DEVICE_ACTION_SUSPEND); in runtime_suspend()
87 pm->base.usage++; in runtime_suspend()
91 pm->base.state = PM_DEVICE_STATE_SUSPENDED; in runtime_suspend()
108 ret = pm->base.action_cb(pm->dev, PM_DEVICE_ACTION_SUSPEND); in runtime_suspend_work()
112 pm->base.usage++; in runtime_suspend_work()
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| /Zephyr-Core-3.6.0/drivers/regulator/ |
| D | regulator_nxp_vref.c | 26 VREF_Type *base; member
35 VREF_Type *const base = config->base; in regulator_nxp_vref_enable() local
37 volatile uint32_t *const csr = &base->CSR; in regulator_nxp_vref_enable()
59 VREF_Type *const base = config->base; in regulator_nxp_vref_disable() local
65 base->CSR &= ~(VREF_CSR_BUF21EN_MASK | VREF_CSR_HCBGEN_MASK | VREF_CSR_LPBGEN_MASK); in regulator_nxp_vref_disable()
73 VREF_Type *const base = config->base; in regulator_nxp_vref_set_mode() local
74 uint32_t csr = base->CSR; in regulator_nxp_vref_set_mode()
100 base->CSR = csr; in regulator_nxp_vref_set_mode()
110 VREF_Type *const base = config->base; in regulator_nxp_vref_get_mode() local
111 uint32_t csr = base->CSR; in regulator_nxp_vref_get_mode()
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| /Zephyr-Core-3.6.0/drivers/i3c/ |
| D | i3c_mcux.c | 71 I3C_Type *base; member
234 * @param base Pointer to controller registers.
238 static uint32_t mcux_i3c_interrupt_disable(I3C_Type *base) in mcux_i3c_interrupt_disable() argument
240 uint32_t intmask = base->MINTSET; in mcux_i3c_interrupt_disable()
242 base->MINTCLR = intmask; in mcux_i3c_interrupt_disable()
250 * @param base Pointer to controller registers.
254 static void mcux_i3c_interrupt_enable(I3C_Type *base, uint32_t mask) in mcux_i3c_interrupt_enable() argument
256 base->MINTSET = mask; in mcux_i3c_interrupt_enable()
267 static bool mcux_i3c_has_error(I3C_Type *base) in mcux_i3c_has_error() argument
271 mstatus = base->MSTATUS; in mcux_i3c_has_error()
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| /Zephyr-Core-3.6.0/soc/arm/nxp_imx/rt6xx/ |
| D | flash_clock_setup.c | 17 static void flash_deinit(FLEXSPI_Type *base) in flash_deinit() argument
20 while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && in flash_deinit()
21 (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) { in flash_deinit()
24 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in flash_deinit()
27 static void flash_init(FLEXSPI_Type *base) in flash_init() argument
35 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in flash_init()
37 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in flash_init()
38 while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) { in flash_init()
42 if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK)) { in flash_init()
43 lastStatus = base->STS2; in flash_init()
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| /Zephyr-Core-3.6.0/tests/unit/timeutil/ |
| D | test_sync.c | 50 zassert_equal(ss.base.ref, 0, in test_state_update()
51 "unexpected base ref"); in test_state_update()
59 zassert_equal(ss.base.ref, 1, in test_state_update()
60 "base not updated"); in test_state_update()
69 zassert_equal(ss.base.ref, 1, in test_state_update()
70 "unexpected base ref"); in test_state_update()
71 zassert_equal(ss.base.local, 0, in test_state_update()
72 "unexpected base local"); in test_state_update()
87 zassert_equal(ss.base.ref, 1, in test_state_update()
88 "unexpected base ref"); in test_state_update()
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