Searched full:armv7 (Results 1 – 25 of 265) sorted by relevance
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| /Zephyr-Core-3.6.0/arch/arm/core/mmu/ |
| D | Kconfig | 2 # ARMv7 Memory Management Unit (MMU) configuration options
11 bool "ARMv7 Cortex-A MMU Support"
18 The current CPU has an ARMv7 Memory Management Unit.
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| /Zephyr-Core-3.6.0/arch/arm/core/cortex_m/ |
| D | Kconfig | 102 Trace (DWT) unit specified by the ARMv7-M and above.
105 from the DWT specified by the ARMv7-M and above in terms of both feature
118 Always present in CPUs that implement the ARMv7-M or
128 in CPUs implementing the ARMv7-M or ARMv8-M architectures.
207 This option signifies the use of an ARMv7-M processor
215 - ARMv7-M compatibility requires the Main Extension.
219 with ARMv7-M.
231 not present in the ARMv7-M architecture.
257 This option signifies the use of an ARMv7-M processor
423 implementation (1 comparator for ARMv7-M, 2 comparators
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| /Zephyr-Core-3.6.0/arch/arm/core/mpu/ |
| D | arm_mpu_v7_internal.h | 21 /* No specific configuration at init for ARMv7-M MPU. */ in mpu_init()
117 /* in ARMv7-M MPU the base address is not required in get_region_attr_from_mpu_partition_info()
137 * Trivial for ARMv7-M MPU, where dynamic memory areas are programmed
146 * In ARMv7-M MPU this is bit AP[1].
227 /* In ARMv7-M architecture the static regions are in mpu_configure_static_mpu_regions()
254 /* In ARMv7-M architecture the dynamic regions are in mpu_configure_dynamic_mpu_regions()
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| D | Kconfig | 21 The ARMv6-M and ARMv7-M MPU architecture requires a power-of-two
94 MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT(ARMv7-M) sometimes cause memory
98 and sub-regions(ARMv7-M) to cover this feature.
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| /Zephyr-Core-3.6.0/cmake/toolchain/llvm/ |
| D | target.cmake | 11 # ARMv8-M mainline is ARMv7-M with additional features from ARMv8-M.
17 # ARMV7_M_ARMV8_M_MAINLINE means that ARMv7-M or backward compatible ARMv8-M
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| /Zephyr-Core-3.6.0/arch/arm/core/cortex_a_r/ |
| D | prep_c.c | 95 * comp. ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition, in z_arm_floating_point_init()
115 * comp. ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition, in z_arm_floating_point_init()
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| D | Kconfig | 114 This option signifies the use of an ARMv7-R processor
118 The Armv7-R architecture implements a traditional Arm architecture with
127 This option signifies the use of an ARMv7-R processor
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| /Zephyr-Core-3.6.0/dts/bindings/mmu_mpu/ |
| D | arm,armv7m-mpu.yaml | 1 description: ARMv7-M Memory Protection Unit (MPU)
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| /Zephyr-Core-3.6.0/dts/bindings/debug/ |
| D | arm,armv7m-itm.yaml | 5 ARMv7 instrumentation trace macrocell. Used for single wire output (SWO)
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| /Zephyr-Core-3.6.0/include/zephyr/arch/arm/mmu/ |
| D | arm_mmu.h | 2 * ARMv7 MMU support
15 * ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition,
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| /Zephyr-Core-3.6.0/dts/bindings/timer/ |
| D | arm,armv7m-systick.yaml | 4 description: ARMv7-M System Tick
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| /Zephyr-Core-3.6.0/soc/arm/nxp_kinetis/k6x/ |
| D | README.txt | 5 standard ARMv7-M SRAM base address of 0x20000000 is supported.
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| /Zephyr-Core-3.6.0/dts/bindings/interrupt-controller/ |
| D | arm,v7m-nvic.yaml | 1 description: ARMv7-M NVIC (Nested Vectored Interrupt Controller)
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| /Zephyr-Core-3.6.0/dts/arm/infineon/psoc6/mpns/ |
| D | CY8C6245FNI_S3D71.dtsi | 8 #include <arm/armv7-m.dtsi>
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| D | CY8C6245LQI_S3D02.dtsi | 8 #include <arm/armv7-m.dtsi>
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| D | CY8C6245LQI_S3D12.dtsi | 8 #include <arm/armv7-m.dtsi>
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| D | CY8C6245LQI_S3D62.dtsi | 8 #include <arm/armv7-m.dtsi>
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| D | CY8C6245LQI_S3D72.dtsi | 8 #include <arm/armv7-m.dtsi>
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| D | CY8C6247BFI_D54.dtsi | 8 #include <arm/armv7-m.dtsi>
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| D | CY8C6247BZI_AUD54.dtsi | 8 #include <arm/armv7-m.dtsi>
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| D | CY8C6247BZI_D34.dtsi | 8 #include <arm/armv7-m.dtsi>
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| D | CY8C6247BZI_D44.dtsi | 8 #include <arm/armv7-m.dtsi>
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| D | CY8C6247BZI_D54.dtsi | 8 #include <arm/armv7-m.dtsi>
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| D | CY8C6247FDI_D02.dtsi | 8 #include <arm/armv7-m.dtsi>
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| D | CY8C6247WI_D54.dtsi | 8 #include <arm/armv7-m.dtsi>
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