| /Zephyr-Core-3.5.0/arch/xtensa/core/ |
| D | debug_helpers_asm.S | 24 * Use a6 and a7 as scratch */
28 /* Load i PC in a7 */
29 l32i a7, a6, ___xtensa_irq_bsa_t_pc_OFFSET
31 s32i a7, a2, 0
32 /* Load value for (i-1) PC, which return address of i into a7 */
33 l32i a7, a6, ___xtensa_irq_bsa_t_a0_OFFSET
35 s32i a7, a4, 0
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| D | window_vectors.S | 124 * a0-a7 are registers to be saved;
142 s32e a7, a0, -20 /* save a7 to call[j]'s stack frame */
153 * a0-a7 are undefined, must be reloaded with call[i].reg[0..7];
165 l32e a7, a1, -12 /* a7 <- call[i-1]'s sp
168 l32e a4, a7, -32 /* restore a4 from call[i]'s stack frame */
169 l32e a5, a7, -28 /* restore a5 from call[i]'s stack frame */
170 l32e a6, a7, -24 /* restore a6 from call[i]'s stack frame */
171 l32e a7, a7, -20 /* restore a7 from call[i]'s stack frame */
200 s32e a7, a0, -36 /* save a7 to end of call[j]'s stack frame */
233 l32e a7, a11, -36 /* restore a7 from end of call[i]'s stack frame */
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| D | crt1.S | 47 # define ARG2 a7 /* 2nd outgoing call argument */
162 * a7 = pointer to end of table
168 movi a7, _bss_table_end
169 bgeu a6, a7, .L3zte
191 bltu a6, a7, .L0zte /* loop until end of table of *.bss sections */
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| /Zephyr-Core-3.5.0/include/zephyr/arch/arm64/ |
| D | arm-smccc.h | 12 * @a0-a7 result values from registers 0 to 7
22 unsigned long a7; member
37 * @param a1-a7 parameters registers
43 unsigned long a6, unsigned long a7,
50 * @param a1-a7 parameters registers
56 unsigned long a6, unsigned long a7,
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| /Zephyr-Core-3.5.0/boards/arm/arty/ |
| D | Kconfig.board | 7 bool "Digilent Arty A7 ARM DesignStart Cortex-M1"
11 bool "Digilent Arty A7 ARM DesignStart Cortex-M3"
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| D | arty_a7_arm_designstart_m1.yaml | 2 name: Digilent Arty A7 ARM DesignStart Cortex-M1
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| D | arty_a7_arm_designstart_m3.yaml | 2 name: Digilent Arty A7 ARM DesignStart Cortex-M3
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| D | arty_a7_arm_designstart_m1.dts | 12 model = "Digilent Arty A7 ARM DesignStart Cortex-M1";
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| D | arty_a7_arm_designstart_m3.dts | 12 model = "Digilent Arty A7 ARM DesignStart Cortex-M3";
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| /Zephyr-Core-3.5.0/dts/bindings/gpio/ |
| D | arduino-nano-header-r3.yaml | 12 signals labeled from A0 through A7, as well a digital signal D13. The
17 correspond to A0 through A7, as depicted below.
23 2 D2 A7/D21 21
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| /Zephyr-Core-3.5.0/boards/riscv/litex_vexriscv/doc/ |
| D | index.rst | 19 `Digilent Arty A7-35T or A7-100T Development Boards
20 <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists>`_
47 bitstream for the FPGA on a Digilent Arty A7-35 Board or SDI-MIPI Video Converter. This can be achi…
70 …Generating the bitstream for the Digilent Arty A7-35 Board requires F4PGA toolchain installation. …
90 #. Set up the F4PGA environment (for the Digilent Arty A7-35 Board):
104 ./make.py --board=arty --variant=a7-35 --build --toolchain=symbiflow
110 ./make.py --board=arty --variant=a7-100 --build --toolchain=symbiflow
170 To upload the bitstream to Digilent Arty A7-35 you can use `xc3sprog <https://github.com/matrix-io/…
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| /Zephyr-Core-3.5.0/arch/xtensa/include/ |
| D | xtensa-asm2-context.h | 48 * - Saved A7 \
180 uintptr_t a7; member
201 uintptr_t a7; member
209 * Interrupt stack frame containing A0 - A7.
217 uintptr_t a7; member
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| /Zephyr-Core-3.5.0/arch/riscv/core/ |
| D | coredump.c | 27 uint32_t a7; member
79 arch_blk.r.a7 = esf->a7; in arch_coredump_info_dump()
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| /Zephyr-Core-3.5.0/boards/arm/pico_pi_m4/doc/ |
| D | index.rst | 9 The i.MX7D SoC is a Hybrid multi-core processor composed of Single Cortex A7
12 communicate with the A7 core (running Linux) via RPmsg.
38 - CPU i.MX7 Dual with a Single Cortex A7 (1 GHz) core and
42 - RAM -> A7: 4GB
44 - Flash -> A7: 8GB eMMC
115 the A7 core. The A7 core is responsible to load the M4 binary application into
118 The A7 can perform these steps at bootloader level or after the Linux system
121 The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and
125 | Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size …
169 Below you will find the instructions to load and run Zephyr on M4 from A7 using
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/stm32mp157c_dk2/doc/ |
| D | stm32mp157_dk2.rst | 10 multi-core processor,composed of a dual Cortex®-A7 and a single Cortex®-M4 core.
17 - Arm®-based dual Cortex®-A7 32 bits
63 - 32-bit dual-core Arm® Cortex®-A7
137 - 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor)
212 by the Linux Remoteproc Framework on Cortex®-A7 core. In order to keep the UART7
222 started by the Cortex®-A7 core. The Cortex®-A7 core is responsible to load the
224 The Cortex®-A7 can perform these steps at bootloader level or after the Linux
229 These are the memory mappings for Cortex®-A7 and Cortex®-M4:
232 | Region | Cortex®-A7 | Cortex®-M4 | Size |
250 environment. The firmware must first be loaded by the Cortex®-A7. Developer
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| /Zephyr-Core-3.5.0/boards/arm/96b_avenger96/doc/ |
| D | index.rst | 10 multi-core processor, composed of a dual Cortex®-A7 and a single Cortex®-M4
58 - 32-bit dual-core Arm® Cortex®-A7
127 - 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor)
194 on Cortex®-A7 core. Alternatively, Zephyr console output can be assigned to
204 started by the Cortex®-A7 core. The Cortex®-A7 core is responsible to load the
206 The Cortex®-A7 can perform these steps at bootloader level or after the Linux
211 These are the memory mappings for Cortex®-A7 and Cortex®-M4:
214 | Region | Cortex®-A7 | Cortex®-M4 | Size |
232 environment. The firmware must first be loaded by the Cortex®-A7. Developer
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| /Zephyr-Core-3.5.0/boards/arm/warp7_m4/doc/ |
| D | index.rst | 9 The i.MX7S SoC is a Hybrid multi-core processor composed of Single Cortex A7
12 communicate with the A7 core (running Linux) via RPmsg.
38 - Debug USB exposing two UARTs (UART1 for A7 and UART2 for M4)
46 - CPU i.MX7 Solo with a Single Cortex A7 (800MHz) core and
50 - RAM -> A7: 4GB (Kingston 08EMCP04)
52 - Flash -> A7: 8GB eMMC (Kingston 08EMCP04)
148 the A7 core. The A7 core is responsible to load the M4 binary application into
151 The A7 can perform these steps at bootloader level or after the Linux system
154 The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and
158 | Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size …
[all …]
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| /Zephyr-Core-3.5.0/arch/xtensa/core/startup/ |
| D | reset-vector.S | 111 rer a7, a2
113 extui a4, a7, 1, 2
230 * effect, registers a3, a5, a7 are now preloaded with values
234 * a7 - contents of PWRSTAT register
243 movi a7, PWRSTAT_WAKEUP_RESET
246 bbci.l a7, PWRSTAT_WAKEUP_RESET_SHIFT, 1f
249 addi a5, a7, - PWRSTAT_WAKEUP_RESET
251 movnez a7, a5, a4
256 bbci.l a7, PWRSTAT_CACHES_LOST_POWER_SHIFT, .Lpso_restore
329 /* Here, a7 still contains status from the power status register,
[all …]
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| /Zephyr-Core-3.5.0/scripts/coredump/gdbstubs/arch/ |
| D | xtensa.py | 291 A7 = 96 variable in GdbRegDef_Sample_Controller.RegNum
325 A7 = 164 variable in GdbRegDef_ESP32.RegNum
357 A7 = 162 variable in GdbRegDef_ESP32S2.RegNum
387 A7 = 219 variable in GdbRegDef_ESP32S3.RegNum
428 A7 = 165 variable in GdbRegDef_Intel_Adsp_CAVS_Zephyr.RegNum
468 A7 = 263 variable in GdbRegDef_Intel_Adsp_CAVS_XCC.RegNum
503 A7 = 112 variable in GdbRegDef_DC233C.RegNum
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| D | risc_v.py | 35 A7 = 17 variable in RegNum
85 self.registers[RegNum.A7] = tu[12]
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| /Zephyr-Core-3.5.0/boards/arm/colibri_imx7d_m4/doc/ |
| D | index.rst | 9 The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual Cortex A7
12 communicate with the A7 core (running Linux) via RPmsg.
22 - i.MX7 Single/Dual Cortex A7 (800MHz/1.0GHz) core and Single Cortex M4 (200MHz) core
26 - RAM -> A7: 256MB, 512MB and 1GB
28 - Flash -> A7: 4Gb eMMC and 512Mb NAND
137 the A7 core. The A7 core is responsible to load the M4 binary application into the
140 The A7 can perform these steps at bootloader level or after the Linux system has
143 The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4:
146 | Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size …
192 Below you will find the instructions to load and run Zephyr on M4 from A7 using u-boot.
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/sip_svc/ |
| D | sip_svc_driver.h | 74 unsigned long *a7, char *buf, size_t size);
264 * @param a7 Argument 7 for supervisory call.
273 unsigned long *a7, char *buf, size_t size);
278 unsigned long *a7, char *buf, size_t size) in z_impl_sip_svc_plat_async_res_req() argument
292 __ASSERT(a7, "a7 shouldn't be NULL"); in z_impl_sip_svc_plat_async_res_req()
295 return api->sip_svc_plat_async_res_req(dev, a0, a1, a2, a3, a4, a5, a6, a7, buf, size); in z_impl_sip_svc_plat_async_res_req()
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| D | sip_svc_proto.h | 114 * a0 - a7
115 * - User input data to be filled into a0-a7 registers when trigger
142 unsigned long a7; member
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| /Zephyr-Core-3.5.0/boards/arm/96b_meerkat96/doc/ |
| D | index.rst | 10 composed of a dual Cortex®-A7 and a single Cortex®-M4 core.
50 - Dual Cortex A7 (800MHz/1.0GHz) core and Single Cortex M4 (200MHz) core
55 - Internal RAM -> A7: 256KB SRAM
153 to be started by the A7 core. The A7 core is responsible to load the M4 binary
155 Stack Pointer, and get the M4 out of reset. The A7 can perform these steps at
158 The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4:
161 | Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size …
205 A7 using u-boot.
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| /Zephyr-Core-3.5.0/drivers/sip_svc/ |
| D | sip_smc_intel_socfpga.c | 120 unsigned long *a7, char *buf, size_t size) in intel_sip_smc_plat_async_res_req() argument
202 LOG_DBG("\tres->a7 %08lx", res->a7); in intel_sip_secure_monitor_call()
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