1/*
2 * Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <arm/armv7-m.dtsi>
9#include "arty_a7_arm_designstart.dtsi"
10
11/ {
12	model = "Digilent Arty A7 ARM DesignStart Cortex-M3";
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			device_type = "cpu";
20			compatible = "arm,cortex-m3";
21			reg = <0>;
22			#address-cells = <1>;
23			#size-cells = <1>;
24
25			mpu: mpu@e000ed90 {
26				compatible = "arm,armv7m-mpu";
27				reg = <0xe000ed90 0x40>;
28				arm,num-mpu-regions = <8>;
29			};
30		};
31	};
32
33	soc {
34		itcm: memory@0 {
35			compatible = "zephyr,memory-region", "arm,itcm";
36			reg = <0x00000000 DT_SIZE_K(32)>;
37			zephyr,memory-region = "ITCM";
38		};
39
40		dtcm: memory@20000000 {
41			compatible = "zephyr,memory-region", "arm,dtcm";
42			reg = <0x20000000 DT_SIZE_K(32)>;
43			zephyr,memory-region = "DTCM";
44		};
45
46		bram0: memory@60000000 {
47			compatible = "mmio-sram";
48			reg = <0x60000000 DT_SIZE_K(8)>;
49		};
50	};
51};
52
53&nvic {
54	arm,num-irq-priority-bits = <3>;
55};
56