| /Zephyr-Core-3.5.0/arch/xtensa/core/ |
| D | xtensa-asm2-util.S | 52 mov a3, a1 /* Stash our original stack pointer */
61 addi a1, a1, -16
62 s32i a4, a1, 0
63 s32i a5, a1, 4
64 s32i a6, a1, 8
65 s32i a7, a1, 12
68 addi a1, a1, -16
69 s32i a8, a1, 0
70 s32i a9, a1, 4
71 s32i a10, a1, 8
[all …]
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| D | window_vectors.S | 30 * all the registers from call[i+1]'s window. In particular, a0 and a1 must be
57 s32e a1, a5, -12 /* save a1 to call[j+1]'s stack frame */
79 l32e a1, a5, -12 /* restore a1 from call[i+1]'s stack frame */
134 l32e a0, a1, -12 /* a0 <- call[j-1]'s sp
136 s32e a1, a9, -12 /* save a1 to call[j+1]'s stack frame */
163 l32e a1, a9, -12 /* restore a1 from call[i+1]'s stack frame */
165 l32e a7, a1, -12 /* a7 <- call[i-1]'s sp
192 l32e a0, a1, -12 /* a0 <- call[j-1]'s sp
194 s32e a1, a13, -12 /* save a1 to call[j+1]'s stack frame */
225 l32e a1, a13, -12 /* restore a1 from call[i+1]'s stack frame */
[all …]
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| /Zephyr-Core-3.5.0/arch/xtensa/include/ |
| D | xtensa-asm2-s.h | 99 * area pointed to by the current stack pointer A1. The Floating-Point
106 s32i a0, a1, ___xtensa_irq_bsa_t_fcr_OFFSET
108 s32i a0, a1, ___xtensa_irq_bsa_t_fsr_OFFSET
109 ssi f0, a1, ___xtensa_irq_bsa_t_fpu0_OFFSET
110 ssi f1, a1, ___xtensa_irq_bsa_t_fpu1_OFFSET
111 ssi f2, a1, ___xtensa_irq_bsa_t_fpu2_OFFSET
112 ssi f3, a1, ___xtensa_irq_bsa_t_fpu3_OFFSET
113 ssi f4, a1, ___xtensa_irq_bsa_t_fpu4_OFFSET
114 ssi f5, a1, ___xtensa_irq_bsa_t_fpu5_OFFSET
115 ssi f6, a1, ___xtensa_irq_bsa_t_fpu6_OFFSET
[all …]
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| /Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/gd32vf103/ |
| D | entry.S | 17 li a1, 1
18 slli a1, a1, 29
19 bleu a1, a0, _start0800
20 srli a1, a1, 2
21 bleu a1, a0, _start0800
23 add a0, a0, a1
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| /Zephyr-Core-3.5.0/include/zephyr/arch/riscv/ |
| D | syscall.h | 45 register unsigned long a1 __asm__ ("a1") = arg2; in arch_syscall_invoke6()
54 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), in arch_syscall_invoke6()
66 register unsigned long a1 __asm__ ("a1") = arg2; in arch_syscall_invoke5()
74 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (t0) in arch_syscall_invoke5()
84 register unsigned long a1 __asm__ ("a1") = arg2; in arch_syscall_invoke4()
91 : "r" (a1), "r" (a2), "r" (a3), "r" (t0) in arch_syscall_invoke4()
101 register unsigned long a1 __asm__ ("a1") = arg2; in arch_syscall_invoke3()
107 : "r" (a1), "r" (a2), "r" (t0) in arch_syscall_invoke3()
116 register unsigned long a1 __asm__ ("a1") = arg2; in arch_syscall_invoke2()
121 : "r" (a1), "r" (t0) in arch_syscall_invoke2()
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| /Zephyr-Core-3.5.0/arch/riscv/core/ |
| D | pmp.S | 19 * unsigned int end, // a1
53 beq t1, a1, pmpaddr_done
63 * a1 = (a1 + RV_REGSIZE - 1) / RV_REGSIZE
69 addi a1, a1, RV_REGSIZE - 1
70 srli a1, a1, RV_REGSHIFT
82 beq a0, a1, pmpcfg_done
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| D | semihost.c | 24 register void *a1 __asm__ ("a1") = args; in semihost_exec()
34 : "=r" (ret) : "r" (a0), "r" (a1) : "memory"); in semihost_exec()
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| D | switch.S | 41 DO_CALLEE_SAVED(sr, a1)
44 sr sp, _thread_offset_to_sp(a1)
47 sr a1, ___thread_t_switch_handle_OFFSET(a1)
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| D | coredump.c | 20 uint32_t a1; member
68 arch_blk.r.a1 = esf->a1; in arch_coredump_info_dump()
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| D | isr.S | 34 RV_E( op a1, __z_arch_esf_t_a1_OFFSET(sp) );\
351 lr a1, __z_arch_esf_t_a1_OFFSET(sp)
361 /* Handle RV_ECALL_RUNTIME_EXCEPT. Retrieve reason in a0, esf in A1. */
363 1: mv a1, sp
370 * Routine pointer is in saved a0, argument in saved a1
371 * so we load them with a1/a0 (reversed).
373 lr a1, __z_arch_esf_t_a0_OFFSET(sp)
391 jalr ra, a1, 0
422 lr a1, __z_arch_esf_t_a1_OFFSET(sp)
566 lr a1, ___cpu_t_current_OFFSET(s0)
[all …]
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| /Zephyr-Core-3.5.0/tests/lib/cmsis_dsp/common/ |
| D | test_common.h | 30 #define DEFINE_TEST_VARIANT1(suite, name, variant, a1) \ argument
33 test_##name(a1); \
36 #define DEFINE_TEST_VARIANT2(suite, name, variant, a1, a2) \ argument
39 test_##name(a1, a2); \
42 #define DEFINE_TEST_VARIANT3(suite, name, variant, a1, a2, a3) \ argument
45 test_##name(a1, a2, a3); \
48 #define DEFINE_TEST_VARIANT4(suite, name, variant, a1, a2, a3, a4) \ argument
51 test_##name(a1, a2, a3, a4); \
54 #define DEFINE_TEST_VARIANT5(suite, name, variant, a1, a2, a3, a4, a5) \ argument
57 test_##name(a1, a2, a3, a4, a5); \
[all …]
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| /Zephyr-Core-3.5.0/tests/bluetooth/ctrl_sw_privacy_unit/src/ |
| D | main.c | 48 bt_addr_t a1, a2, a3, a4, a5; in helper_prpa_add() local
51 bt_addr_copy(&a1, BT_ADDR_INIT(0x12, 0x13, 0x14, 0x15, 0x16, 0x17)); in helper_prpa_add()
57 prpa_cache_add(&a1); in helper_prpa_add()
58 pos = prpa_cache_find(&a1); in helper_prpa_add()
78 /* adding this should cause a1 to be dropped */ in helper_prpa_add()
84 /* check that a1 can no longer be found */ in helper_prpa_add()
85 pos = prpa_cache_find(&a1); in helper_prpa_add()
91 bt_addr_t a1, a2, a3, a4, a5; in helper_trpa_add() local
94 bt_addr_copy(&a1, BT_ADDR_INIT(0x12, 0x13, 0x14, 0x15, 0x16, 0x17)); in helper_trpa_add()
100 trpa_cache_add(&a1, 0); in helper_trpa_add()
[all …]
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| /Zephyr-Core-3.5.0/include/zephyr/arch/arm64/ |
| D | arm-smccc.h | 16 unsigned long a1; member
37 * @param a1-a7 parameters registers
40 void arm_smccc_hvc(unsigned long a0, unsigned long a1,
50 * @param a1-a7 parameters registers
53 void arm_smccc_smc(unsigned long a0, unsigned long a1,
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| /Zephyr-Core-3.5.0/soc/riscv/riscv-ite/it8xxx2/ |
| D | __arithmetic.S | 31 /* signed 32 bit multiplication. opcode of mul a0,a0,a1 is 0x02b50533 */
34 /* signed 32 bit division. opcode of div a0,a0,a1 is 0x02b54533 */
37 /* unsigned 32 bit division. opcode of divu a0,a0,a1 is 0x02b55533 */
42 * opcode of rem a0,a0,a1 is 0x02b56533
48 * opcode of remu a0,a0,a1 is 0x02b57533
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/common/ |
| D | multiprocessing.c | 77 " movi a1, z_mp_start_cpu \n\t"
78 " l32i a1, a1, 0 \n\t"
79 " l32i a1, a1, 0 \n\t"
81 " sub a2, a2, a1 \n\t"
83 " movi a1, z_mp_stack_top \n\t"
84 " l32i a1, a1, 0 \n\t"
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/ |
| D | power.c | 102 uint32_t a1; member
129 __asm__ volatile("mov %0, a1" : "=r"(core_desc[core_id].a1)); in _save_core_context()
142 __asm__ volatile("mov a1, %0" :: "r"(core_desc[core_id].a1)); in _restore_core_context()
183 " movi a1, 1\n\t"
186 " wsr a1, WINDOWSTART\n\t"
189 " movi a1, z_interrupt_stacks\n\t"
194 " add a1, a1, a2\n\t"
202 " movi a1, 1\n\t" in power_off_exit()
205 " wsr a1, WINDOWSTART\n\t" in power_off_exit()
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| /Zephyr-Core-3.5.0/subsys/bluetooth/crypto/ |
| D | bt_crypto.c | 78 int bt_crypto_f5(const uint8_t *w, const uint8_t *n1, const uint8_t *n2, const bt_addr_le_t *a1, in bt_crypto_f5() argument
89 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* a1 */ in bt_crypto_f5()
110 m[37] = a1->type; in bt_crypto_f5()
111 sys_memcpy_swap(m + 38, a1->a.val, 6); in bt_crypto_f5()
140 const uint8_t *iocap, const bt_addr_le_t *a1, const bt_addr_le_t *a2, in bt_crypto_f6() argument
152 LOG_DBG("a1 %s", bt_hex(a1, 7)); in bt_crypto_f6()
160 m[51] = a1->type; in bt_crypto_f6()
161 memcpy(m + 52, a1->a.val, 6); in bt_crypto_f6()
162 sys_memcpy_swap(m + 52, a1->a.val, 6); in bt_crypto_f6()
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| D | bt_crypto.h | 52 * @param[in] a1 56-bit
60 int bt_crypto_f5(const uint8_t *w, const uint8_t *n1, const uint8_t *n2, const bt_addr_le_t *a1,
73 * @param[in] a1 56-bit
81 const uint8_t *iocap, const bt_addr_le_t *a1, const bt_addr_le_t *a2,
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| /Zephyr-Core-3.5.0/drivers/sip_svc/ |
| D | sip_smc_intel_socfpga.c | 93 /* Assign the trans id into intel smc header a1 */ in intel_sip_smc_plat_update_trans_id()
94 SMC_PLAT_PROTO_HEADER_SET_TRANS_ID(request->a1, trans_id); in intel_sip_smc_plat_update_trans_id()
118 unsigned long *a1, unsigned long *a2, unsigned long *a3, in intel_sip_smc_plat_async_res_req() argument
126 *a1 = 0; in intel_sip_smc_plat_async_res_req()
196 LOG_DBG("\tres->a1 %08lx", res->a1); in intel_sip_secure_monitor_call()
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| /Zephyr-Core-3.5.0/dts/bindings/gpio/ |
| D | arduino-mkr-header.yaml | 10 A1 to A6 is Analog input. The outside pin is AREF.
23 16 A1/D16 VCC -
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| /Zephyr-Core-3.5.0/samples/arch/mpu/mpu_test/ |
| D | README.rst | 55 <err> os: r0/a1: 0x00009a5c r1/a2: 0x00000008 r2/a3: 0x20001aa8
71 <err> os: r0/a1: 0x00000000 r1/a2: 0x0000000e r2/a3: 0x0badc0de
85 <err> os: r0/a1: 0x00009a5c r1/a2: 0x00000001 r2/a3: 0x20001aa8
113 <err> os: r0/a1: 0x0800a54c r1/a2: 0x00000008 r2/a3: 0x08003
126 <err> os: r0/a1: 0x00000000 r1/a2: 0x0000000e r2/a3: 0x0000e
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| /Zephyr-Core-3.5.0/tests/arch/arm/arm_interrupt/ |
| D | README.txt | 61 E: r0/a1: 0x20000000 r1/a2: 0x00000000 r2/a3: 0x20001e40
75 E: r0/a1: 0x00000003 r1/a2: 0x200020b8 r2/a3: 0x00000003
84 E: r0/a1: 0x00000004 r1/a2: 0x200020b8 r2/a3: 0x00000004
96 E: r0/a1: 0x00000004 r1/a2: 0x000000cf r2/a3: 0x00000000
108 E: r0/a1: 0x00000004 r1/a2: 0x00000017 r2/a3: 0x00000000
119 E: r0/a1: 0xdde8d9e7 r1/a2: 0x5510538d r2/a3: 0x00000d74
132 E: r0/a1: 0x00000000 r1/a2: 0x00000001 r2/a3: 0x00000002
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| /Zephyr-Core-3.5.0/scripts/tests/twister/test_data/quarantines/ |
| D | basic.yaml | 6 comment: "a1 on board_1 and board_3"
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| /Zephyr-Core-3.5.0/scripts/coredump/gdbstubs/arch/ |
| D | xtensa.py | 285 A1 = 90 variable in GdbRegDef_Sample_Controller.RegNum
319 A1 = 158 variable in GdbRegDef_ESP32.RegNum
351 A1 = 156 variable in GdbRegDef_ESP32S2.RegNum
381 A1 = 213 variable in GdbRegDef_ESP32S3.RegNum
410 # G packet to include up to A1, which fixed the issue.
422 A1 = 159 variable in GdbRegDef_Intel_Adsp_CAVS_Zephyr.RegNum
462 A1 = 257 variable in GdbRegDef_Intel_Adsp_CAVS_XCC.RegNum
497 A1 = 106 variable in GdbRegDef_DC233C.RegNum
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| /Zephyr-Core-3.5.0/boards/shields/x_nucleo_idb05a1/doc/ |
| D | index.rst | 37 Also shield expects SPI CS to be available on Arduino pin A1 instead of usual
39 This is not a problem as CS signal is software driven gpio on Arduino A1
50 - CS: To use D10 instead of A1, remove R2 and add R7
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