| /Zephyr-Core-3.5.0/subsys/bluetooth/controller/ |
| D | Kconfig.df | 273 prompt "IQ samples 12 bit to 8 bit conversion approach"
278 bool "Conversion of IQ samples to 8 bits wide by 4 bits shift"
282 Bluetooth 5.3 Core Specification defines IQ samples to be 8 bits wide: Vol 4, Part E
284 8 bits by ordinary right shift operation by 4 bits. That means there is loss in accuracy
285 since only the 8 MSB are used.
288 bool "Conversion of IQ samples to 8 bits wide by 2 bits shift"
292 Bluetooth 5.3 Core Specification defines IQ samples to be 8 bits wide: Vol 4, Part E
294 8 bits by ordinary right shift operation by 2 bits and a cast to int8_t. That means there
299 bool "Conversion of IQ samples to 8 bits wide by use of 8 LSB"
303 Bluetooth 5.3 Core Specification defines IQ samples to be 8 bits wide: Vol 4, Part E
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| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/interrupt-controller/ |
| D | mchp-xec-ecia.h | 11 * g = bits[0:4], GIRQ number in [8, 26]
12 * gb = bits[12:8], peripheral source bit position [0, 31] in the GIRQ
13 * na = bits[23:16], aggregated GIRQ NVIC number
14 * nd = bits[31:24], direct NVIC number. For sources without a direct
20 (((g) & 0x1f) + (((gb) & 0x1f) << 8) + (((na) & 0xff) << 16) + \
25 #define MCHP_XEC_ECIA_GIRQ_POS(e) (((e) >> 8) & 0x1f)
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/mfd/ |
| D | npm1300.h | 41 * @param base Register base address (bits 15..8 of 16-bit address)
42 * @param offset Register offset address (bits 7..0 of 16-bit address)
55 * @param base Register base address (bits 15..8 of 16-bit address)
56 * @param offset Register offset address (bits 7..0 of 16-bit address)
67 * @param base Register base address (bits 15..8 of 16-bit address)
68 * @param offset Register offset address (bits 7..0 of 16-bit address)
79 * @param base Register base address (bits 15..8 of 16-bit address)
80 * @param offset Register offset address (bits 7..0 of 16-bit address)
90 * @brief Update selected bits in npm1300 register
93 * @param base Register base address (bits 15..8 of 16-bit address)
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| /Zephyr-Core-3.5.0/drivers/interrupt_controller/ |
| D | Kconfig.multilevel | 22 int "Total number of first level interrupt bits"
24 default 8
26 The number of bits to use of the 32 bit interrupt mask for first
56 range 1 8
65 int "Total number of second level interrupt bits"
67 default 8
69 The number of bits to use of the 32 bit interrupt mask for second
101 range 1 8
119 int "Total number of third level interrupt bits"
121 default 8
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| /Zephyr-Core-3.5.0/dts/bindings/dma/ |
| D | gd,gd32-dma-v1.yaml | 27 - 0x0: 8 bits
28 - 0x1: 16 bits
29 - 0x2: 32 bits
33 - 0x0: 8 bits
34 - 0x1: 16 bits
35 - 0x2: 32 bits
82 For example, In the case of data-width is 'byte' and burst-length is 8.
83 If the fifo-threshold is a 2-word case, it runs one burst transfer to transfer 8 bytes.
84 Or the fifo-threshold is a 4-word case, runs two times burst transfer to transferring 8 bytes each
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| D | st,stm32-bdma.yaml | 8 capable of supporting 5 or 6 or 7 or 8 independent BDMA channels.
9 Each channel can have up to 8 requests.
29 0x0: Byte (8 bits)
30 0x1: Half-word (16 bits)
31 0x2: Word (32 bits)
34 0x0: Byte (8 bits)
35 0x1: Half-word (16 bits)
36 0x2: Word (32 bits)
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| D | st,stm32u5-dma.yaml | 21 2. slot: DMA periph request ID, which is written in the REQSEL bits of the CxTR2
37 0x0: Byte (8 bits)
38 0x1: Half-word (16 bits)
39 0x2: Word (32 bits)
42 0x0: Byte (8 bits)
43 0x1: Half-word (16 bits)
44 0x2: Word (32 bits)
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| D | gd,gd32-dma.yaml | 25 - 0x0: 8 bits
26 - 0x1: 16 bits
27 - 0x2: 32 bits
31 - 0x0: 8 bits
32 - 0x1: 16 bits
33 - 0x2: 32 bits
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| D | st,stm32-dma-v2.yaml | 11 capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
38 0x0: STM32_DMA_PERIPH_8BITS: Byte (8 bits)
39 0x1: STM32_DMA_PERIPH_16BITS: Half-word (16 bits)
40 0x2: STM32_DMA_PERIPH_32BITS: Word (32 bits)
43 0x0: STM32_DMA_MEM_8BITS: Byte (8 bits)
44 0x1: STM32_DMA_MEM_16BITS: Half-word (16 bits)
45 0x2: STM32_DMA_MEM_32BITS: Word (32 bits)
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| D | st,stm32-dmamux.yaml | 27 0x0: Byte (8 bits)
28 0x1: Half-word (16 bits)
29 0x2: Word (32 bits)
32 0x0: Byte (8 bits)
33 0x1: Half-word (16 bits)
34 0x2: Word (32 bits)
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| D | st,stm32-dma-v2bis.yaml | 32 0x0: STM32_DMA_PERIPH_8BITS: Byte (8 bits)
33 0x1: STM32_DMA_PERIPH_16BITS: Half-word (16 bits)
34 0x2: STM32_DMA_PERIPH_32BITS: Word (32 bits)
37 0x0: STM32_DMA_MEM_8BITS: Byte (8 bits)
38 0x1: STM32_DMA_MEM_16BITS: Half-word (16 bits)
39 0x2: STM32_DMA_MEM_32BITS: Word (32 bits)
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| /Zephyr-Core-3.5.0/dts/bindings/crypto/ |
| D | nordic,nrf-ccm.yaml | 17 length-field-length-8-bits:
21 (8 bits) of the LENGTH field in encrypted/decrypted packets.
22 If not set, only the default length (5 bits) is supported.
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| /Zephyr-Core-3.5.0/subsys/net/ip/ |
| D | 6lo.c | 53 static const uint8_t sa_inline_size_table[] = {16, 8, 2, 0, 0, 8, 2, 0};
59 16, 8, 2, 0, 0, 8, 2, 0, 16, 6, 4, 1, 6
86 if (((iphc >> 8) & NET_6LO_DISPATCH_IPHC_MASK) != in get_ihpc_inlined_size()
244 !memcmp(ctx_6co[i].prefix.s6_addr, addr->s6_addr, 8)) { in get_6lo_context_by_addr()
258 * version: 4 bits, Traffic Class: 8 bits, Flow label: 20 bits
259 * The Traffic Class field in the IPv6 header comprises 6 bits of
260 * Diffserv extension [RFC2474] and 2 bits of Explicit Congestion
379 /* Following 64 bits are 0000:00ff:fe00:XXXX */ in compress_sa()
390 NET_DBG("SAM_01 src 64 bits are inlined"); in compress_sa()
391 /* Remaining 64 bits are in-line */ in compress_sa()
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/misc/ft8xx/ |
| D | ft8xx_common.h | 29 * @brief Write 1 byte (8 bits) to FT8xx memory
37 * @brief Write 2 bytes (16 bits) to FT8xx memory
45 * @brief Write 4 bytes (32 bits) to FT8xx memory
53 * @brief Read 1 byte (8 bits) from FT8xx memory
62 * @brief Read 2 bytes (16 bits) from FT8xx memory
71 * @brief Read 4 bytes (32 bits) from FT8xx memory
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| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/clock/ |
| D | imx_ccm.h | 11 * Define 16 bits clock ID: 0xXXXX
12 * The highest 8 bits is Peripheral ID
13 * The lowest 8 bits is Instance ID
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| /Zephyr-Core-3.5.0/subsys/bluetooth/controller/util/ |
| D | util.c | 24 * @brief Population count: Count the number of bits set to 1
30 * @param octets_len Must not be bigger than 255/8 = 31 bytes
61 * bits.
64 * - It shall have at least three ones in the least significant 8 bits.
66 * bits.
124 if ((bit_idx < 8) && consecutive_bit) { in util_aa_le32()
131 * significant six bits. in util_aa_le32()
149 if (bit_idx < 8) { in util_aa_le32()
157 if (bit_idx < 8) { in util_aa_le32()
186 * significant 16 bits. in util_aa_le32()
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| /Zephyr-Core-3.5.0/drivers/dai/intel/ssp/ |
| D | ssp.h | 35 #define DAI_INTEL_SSP_FIFO_WATERMARK 8
42 #define DAI_INTEL_SSP_DEFAULT_TRY_TIMES 8
64 /* SSCR0 bits */
74 #define SSCR0_SCR_MASK DAI_INTEL_SSP_MASK(19, 8)
75 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x)
85 /* SSCR1 bits */
125 /* SSR bits */
134 /* SSPSP bits */
139 #define SSPSP_DMYSTRT(x) DAI_INTEL_SSP_SET_BITS(8, 7, x)
155 /* SSTSA bits */
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| /Zephyr-Core-3.5.0/drivers/spi/ |
| D | spi_dw.h | 97 case 8: in reg_read()
111 case 8: in reg_write()
172 /* Common registers settings, bits etc... */
186 #define DW_SPI_CTRLR0_TMOD_SHIFT (8)
203 /* 0x38 represents the bits 8, 16 and 32. Knowing that 24 is bits 8 and 16
204 * These are the bits were when you divide by 8, you keep the result as it is.
209 (((__bpw) / 8) + 1) : \
210 ((__bpw) / 8))
212 /* SSIENR bits */
215 /* CLK_ENA bits */
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| D | spi_pw.h | 50 /* Data size set bits sscr0[3:0] */
59 /* SSP Baud rate sscr0[19:8] */
66 /* [19:8] 12 bits */
67 #define PW_SPI_SCR_MASK (BIT_MASK(12) << 8)
105 /* SPI Tx FIFO Lower Water Mark[13:8] */
106 #define PW_SPI_SITF_LWM_2_ENTRY (BIT(0) << 8)
107 #define PW_SPI_SITF_LWM_3_ENTRY (BIT(1) << 8)
108 #define PW_SPI_SITF_LWM_4_ENTRY ((BIT(1) | BIT(0)) << 8)
124 /* SPI Rx FIFO Level RITF[13:8] */
125 #define PW_SPI_SIRF_SIRFL_MASK (BIT_MASK(6) << 8)
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| /Zephyr-Core-3.5.0/dts/bindings/spi/ |
| D | xlnx,xps-spi-2.00.a.yaml | 20 xlnx,num-ss-bits:
29 Number of slave select bits implemented
31 xlnx,num-transfer-bits:
35 - 8
39 Number of bits per transfer
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| /Zephyr-Core-3.5.0/dts/bindings/sensor/ |
| D | maxim,max31875.yaml | 29 - "8"
37 The number of bits used for each temperature sample.
38 A resolution of 10 bits takes 35ms to convert.
41 10 bits of resolution is the power-on reset configuration.
47 - 8 # 8.75
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| /Zephyr-Core-3.5.0/dts/bindings/serial/ |
| D | uart-controller.yaml | 26 stop-bits:
29 Sets the number of stop bits.
35 data-bits:
38 Sets the number of data bits.
43 - 8
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| /Zephyr-Core-3.5.0/include/zephyr/arch/arm64/ |
| D | tpidrro_el0.h | 9 * @brief tpidrro_el0 bits allocation
12 * CPU's struct _cpu instance. But such a pointer is at least 8-bytes
13 * aligned, and the address space is 48 bits max. That leaves plenty of
14 * free bits for other purposes.
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| /Zephyr-Core-3.5.0/drivers/i2c/ |
| D | i2c_dw_registers.h | 15 /* IC_CON bits */
28 } bits; member
31 /* IC_DATA_CMD bits */
33 #define IC_DATA_CMD_CMD BIT(8)
37 /* DesignWare Interrupt bits positions */
46 #define DW_INTR_STAT_ACTIVITY BIT(8)
61 #define DW_INTR_MASK_ACTIVITY BIT(8)
87 } bits; member
99 } bits; member
112 uint32_t rx_buffer_depth : 8 __packed;
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| /Zephyr-Core-3.5.0/tests/kernel/common/src/ |
| D | bitarray.c | 57 num_bundles = ROUND_UP(ROUND_UP(num_bits, 8) / 8, sizeof(uint32_t)) in validate_bitarray_define()
91 * in the declared array are set as free to represent the number of bits in ZTEST()
141 bundle_idx = bit / (sizeof(ba.bundles[0]) * 8); in ZTEST()
142 bit_idx_in_bundle = bit % (sizeof(ba.bundles[0]) * 8); in ZTEST()
221 * total bits in bit array. Also needs to make sure bits in ZTEST()
290 /* Pre-populate the bits */ in alloc_and_free_predefined()
306 "sys_bitarray_alloc() failed bits comparison"); in alloc_and_free_predefined()
314 "sys_bitarray_alloc() failed bits comparison"); in alloc_and_free_predefined()
320 "sys_bitarray_free() failed bits comparison"); in alloc_and_free_predefined()
325 "sys_bitarray_free() failed bits comparison"); in alloc_and_free_predefined()
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