| /Zephyr-latest/soc/nxp/imx/imx8m/m4_quad/ |
| D | soc.c | 7 #include <zephyr/device.h>
8 #include <fsl_clock.h>
9 #include <fsl_common.h>
10 #include <fsl_rdc.h>
11 #include <zephyr/init.h>
12 #include <zephyr/kernel.h>
13 #include <soc.h>
15 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
71 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
73 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
[all …]
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| /Zephyr-latest/soc/nxp/imx/imx8m/m4_mini/ |
| D | soc.c | 7 #include <zephyr/device.h>
8 #include <fsl_clock.h>
9 #include <fsl_common.h>
10 #include <fsl_rdc.h>
11 #include <zephyr/init.h>
12 #include <zephyr/kernel.h>
13 #include <soc.h>
15 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
108 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
110 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
[all …]
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| /Zephyr-latest/soc/nxp/imx/imx8m/m7/ |
| D | soc.c | 7 #include <zephyr/device.h>
8 #include <fsl_clock.h>
9 #include <fsl_common.h>
10 #include <fsl_rdc.h>
11 #include <zephyr/init.h>
12 #include <zephyr/kernel.h>
13 #include <soc.h>
15 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
111 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
113 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
[all …]
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| /Zephyr-latest/tests/boards/intel_adsp/cache/src/ |
| D | main.c | 7 #include <zephyr/ztest.h>
8 #include <zephyr/cache.h>
9 #include <adsp_memory.h>
33 *uncached = 80; in ZTEST()
36 zassert_equal(*cached, 80, NULL); in ZTEST()
37 zassert_equal(*uncached, 80, NULL); in ZTEST()
43 zassert_equal(*uncached, 80, NULL); in ZTEST()
|
| /Zephyr-latest/tests/net/utils/src/ |
| D | main.c | 9 #include <zephyr/logging/log.h>
12 #include <zephyr/kernel.h>
13 #include <zephyr/ztest_assert.h>
14 #include <zephyr/types.h>
15 #include <stddef.h>
16 #include <string.h>
17 #include <stdio.h>
18 #include <errno.h>
19 #include <zephyr/device.h>
20 #include <zephyr/init.h>
[all …]
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_stm32l4_l5_wb_wl.c | 9 #include <soc.h>
10 #include <stm32_ll_bus.h>
11 #include <stm32_ll_pwr.h>
12 #include <stm32_ll_rcc.h>
13 #include <stm32_ll_utils.h>
14 #include <zephyr/drivers/clock_control.h>
15 #include <zephyr/sys/util.h>
16 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
17 #include <zephyr/sys/time_units.h>
18 #include "clock_stm32_ll_common.h"
[all …]
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| /Zephyr-latest/subsys/logging/backends/ |
| D | log_backend_adsp.c | 7 #include <zephyr/logging/log_backend.h>
8 #include <zephyr/logging/log_core.h>
9 #include <zephyr/logging/log_output.h>
10 #include <zephyr/logging/log_backend_std.h>
36 * 80 bytes seems to catch most sensibly sized log message lines
42 #define LOG_BUF_SIZE 80
|
| /Zephyr-latest/tests/net/socket/getnameinfo/src/ |
| D | main.c | 7 #include <zephyr/logging/log.h>
10 #include <stdio.h>
11 #include <zephyr/ztest_assert.h>
13 #include <zephyr/net/socket.h>
18 char host[80]; in ZTEST_USER()
48 char host[80]; in ZTEST_USER()
|
| /Zephyr-latest/include/zephyr/net/ |
| D | ieee802154_pkt.h | 18 #include <string.h>
20 #include <zephyr/types.h>
34 #define IEEE802154_MAC_RSSI_MAX 254U /* corresponds to 80 dBm */
38 #define IEEE802154_MAC_RSSI_DBM_MAX 80 /* in dBm */
52 * the minimum and maximum values are 0 (–174 dBm) and 254 (80 dBm),
115 * 0 (–174 dBm) to 254 (80 dBm).
132 * 0 (–174 dBm) to 254 (80 dBm).
167 * not available for this packet. Values above 80 dBm will
168 * be mapped to 80 dBm, values below -174 dBm will be mapped
|
| /Zephyr-latest/boards/shields/lcd_par_s035/ |
| D | lcd_par_s035_8080.overlay | 7 #include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
46 frmctl1 = [80 10];
49 pwr1 = [80 64];
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| /Zephyr-latest/soc/microchip/mec/mec172x/reg/ |
| D | mec172x_p80bd.h | 10 #include <stdint.h>
11 #include <stddef.h>
77 /* Capture 32-bit (RO). Current 4-byte Port 80 capture value */
80 /** @brief BIOS Debug Port 80h and Alias port capture registers. */
|
| /Zephyr-latest/doc/build/cmake/ |
| D | index.rst | 65 :width: 80%
91 :file:`build/zephyr/include/generated/zephyr/devicetree_generated.h` header with
95 including the :zephyr_file:`devicetree.h <include/zephyr/devicetree.h>` header,
96 which includes :file:`devicetree_generated.h`.
119 The output from Kconfig is an :file:`autoconf.h` header with preprocessor
122 :file:`autoconf.h` are automatically exposed at compile time, so there is no
151 *offsets.h* (by *gen_offset_header.py*) facilitates this.
162 :width: 80%
177 :width: 80%
207 :width: 80%
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| /Zephyr-latest/tests/subsys/settings/src/ |
| D | settings_empty_lookups.c | 8 #include "settings_test.h"
13 char name[80]; in ZTEST()
|
| D | settings_test_commit.c | 8 #include "settings_test.h"
12 char name[80]; in ZTEST()
|
| D | settings_test_getset_unknown.c | 8 #include "settings_test.h"
9 #include <errno.h>
13 char name[80]; in ZTEST()
|
| D | settings_test_getset_int.c | 8 #include "settings_test.h"
12 char name[80]; in ZTEST()
|
| /Zephyr-latest/samples/net/prometheus/ |
| D | Kconfig | 14 default 80
28 default "dummy_psk.h"
|
| /Zephyr-latest/tests/kernel/fifo/fifo_api/src/ |
| D | test_fifo_cancel.c | 7 #include "test_fifo.h"
44 /* 80 includes generous fuzz factor as k_sleep() will add an extra in tfifo_thread_thread()
49 zassert_true(dur < 80, in tfifo_thread_thread()
|
| /Zephyr-latest/dts/arm/ti/ |
| D | cc1352r.dtsi | 7 #include <mem.h>
12 reg = <0x20000000 DT_SIZE_K(80)>;
|
| /Zephyr-latest/dts/arm/st/h5/ |
| D | stm32h533Xe.dtsi | 6 #include <mem.h>
18 reg = <0x20040000 DT_SIZE_K(80)>;
|
| /Zephyr-latest/drivers/sensor/st/lis3mdl/ |
| D | lis3mdl.h | 10 #include <zephyr/device.h>
11 #include <zephyr/sys/util.h>
12 #include <zephyr/types.h>
13 #include <zephyr/drivers/i2c.h>
14 #include <zephyr/drivers/gpio.h>
15 #include <zephyr/kernel.h>
90 "40", "80", "155", "300", "560", "1000"
101 LIS3MDL_ODR_BITS(0, 7, 0), /* 80 Hz */
|
| /Zephyr-latest/tests/subsys/fs/fat_fs_api/src/ |
| D | main.c | 8 #include <time.h>
10 #include "test_fat.h"
24 return (DWORD)(cal->tm_year - 80) << 25 | (DWORD)(cal->tm_mon + 1) << 21 | in get_fattime()
|
| /Zephyr-latest/soc/atmel/sam/sam4l/ |
| D | soc.h | 20 #include <sam4ls8c.h>
22 #include <sam4ls8b.h>
24 #include <sam4ls8a.h>
26 #include <sam4ls4c.h>
28 #include <sam4ls4b.h>
30 #include <sam4ls4a.h>
32 #include <sam4ls2c.h>
34 #include <sam4ls2b.h>
36 #include <sam4ls2a.h>
38 #include <sam4lc8c.h>
[all …]
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| /Zephyr-latest/drivers/spi/ |
| D | spi_esp32_spim.h | 10 #include <zephyr/drivers/pinctrl.h>
11 #include <hal/spi_hal.h>
13 #include <hal/gdma_hal.h>
25 #define SPI_MASTER_FREQ_80M (APB_CLK_FREQ/1) /* 80MHz */
|
| /Zephyr-latest/tests/kernel/fpu_sharing/generic/src/ |
| D | float_regs_x86_gcc.h | 19 #include <zephyr/toolchain.h>
20 #include "float_context.h"
47 "movdqu 80(%0), %%xmm5\n\t;" in _load_all_float_registers()
91 "movdqu 80(%0), %%xmm5\n\t;" in _load_then_store_all_float_registers()
139 "movdqu %%xmm5, 80(%0)\n\t;" in _store_all_float_registers()
|
