Lines Matching +full:80 +full:h
7 #include <zephyr/device.h>
8 #include <fsl_clock.h>
9 #include <fsl_common.h>
10 #include <fsl_rdc.h>
11 #include <zephyr/init.h>
12 #include <zephyr/kernel.h>
13 #include <soc.h>
15 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
71 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
73 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
77 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
79 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
83 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
85 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
89 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
91 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()