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/Zephyr-latest/samples/drivers/video/capture/
DREADME.rst83 RGBP width [480; 480; 0] height [272; 272; 0]
84 YUYV width [480; 480; 0] height [272; 272; 0]
85 RGBP width [640; 640; 0] height [480; 480; 0]
86 YUYV width [640; 640; 0] height [480; 480; 0]
89 - Default format: RGBP 480x272
93 x_resolution = 480, y_resolution = 272, supported_pixel_formats = 40
/Zephyr-latest/boards/shields/lcd_par_s035/doc/
Dindex.rst9 The LCD-PAR-S035 is a 3.5” 480x320 IPS TFT LCD module with wide viewing angle
40 …sign/design-center/development-boards-and-designs/general-purpose-mcus/3-5-480x320-ips-tft-lcd-mod…
/Zephyr-latest/boards/shields/rtkmipilcdb00000be/
Drtkmipilcdb00000be.overlay37 width = <480>;
45 width = <480>;
/Zephyr-latest/boards/shields/st_b_lcd40_dsi1_mb1166/
Dst_b_lcd40_dsi1_mb1166.overlay28 width = <480>;
40 height = <480>;
Dst_b_lcd40_dsi1_mb1166_a09.overlay28 width = <480>;
40 height = <480>;
/Zephyr-latest/samples/drivers/video/capture_to_lvgl/
DREADME.rst52 [00:00:02.780,000] <inf> main: RGBP width [640; 640; 0] height [480; 480; 0]
62 [00:00:02.780,000] <inf> main: JPEG width [640; 640; 0] height [480; 480; 0]
/Zephyr-latest/tests/arch/x86/info/
Dapp.overlay10 height = <480>;
/Zephyr-latest/samples/modules/lvgl/demos/boards/
Dnative_posix.overlay10 width = <480>;
Dnative_posix_64.overlay10 width = <480>;
/Zephyr-latest/samples/drivers/video/tcpserversink/
DREADME.rst47 Video device detected, format: RGBP 480x272
57 ! videoparse format=rgb16 width=480 height=272 \
/Zephyr-latest/drivers/video/
Dmt9m114.c128 {MT9M114_CAM_OUTPUT_WIDTH, 2, 0x01E0}, /* 480 */
143 {MT9M114_CAM_CROP_WINDOW_HEIGHT, 2, 0x01E0}, /* 480 */
145 {MT9M114_CAM_OUTPUT_HEIGHT, 2, 0x01E0}, /* 480 */
169 {.width = 480, .height = 272, .params = mt9m114_480_272},
170 {.width = 640, .height = 480, .params = mt9m114_640_480},
181 MT9M114_VIDEO_FORMAT_CAP(480, 272, VIDEO_PIX_FMT_RGB565),
182 MT9M114_VIDEO_FORMAT_CAP(480, 272, VIDEO_PIX_FMT_YUYV),
183 MT9M114_VIDEO_FORMAT_CAP(640, 480, VIDEO_PIX_FMT_RGB565),
184 MT9M114_VIDEO_FORMAT_CAP(640, 480, VIDEO_PIX_FMT_YUYV),
537 /* Set default format to 480x272 RGB565 */ in mt9m114_init()
[all …]
/Zephyr-latest/soc/renesas/rz/rzg3s/
DKconfig.defconfig8 default 480
/Zephyr-latest/dts/bindings/clock/
Dst,stm32h7-rcc.yaml20 clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
/Zephyr-latest/tests/lib/heap/
Dtestcase.yaml16 timeout: 480
/Zephyr-latest/drivers/sensor/st/lps25hb/
Dlps25hb.c87 /* val = raw_val / 480 + 42.5 */ in lps25hb_temp_convert()
88 uval = (int32_t)raw_val * 1000000 / 480 + 42500000; in lps25hb_temp_convert()
89 val->val1 = (raw_val * 10 / 480 + 425) / 10; in lps25hb_temp_convert()
/Zephyr-latest/dts/bindings/cpu/
Despressif,riscv.yaml18 320 MHz or 480 MHz.
Despressif,xtensa-lx6.yaml18 320 MHz or 480 MHz.
Despressif,xtensa-lx7.yaml18 320 MHz or 480 MHz.
/Zephyr-latest/boards/shields/ftdi_vm800c/
Dftdi_vm800c.overlay30 hsize = <480>;
/Zephyr-latest/boards/shields/waveshare_epaper/
Dwaveshare_epaper_gdew075t7.overlay28 height = <480>;
/Zephyr-latest/subsys/logging/backends/
DKconfig.net103 default 480 if NET_IPV4
108 The RFC 5426 recommends that for IPv4 the size is 480 octets and for
/Zephyr-latest/boards/shields/rk043fn02h_ct/
Drk043fn02h_ct.overlay32 width = <480>;
/Zephyr-latest/boards/shields/rk043fn66hs_ctg/
Drk043fn66hs_ctg.overlay33 width = <480>;
/Zephyr-latest/soc/microchip/mec/common/
Dsoc_pcr.h33 #define MCHP_XEC_CLK_SLOW_CLK_DIV_100K 480u
/Zephyr-latest/boards/shields/lcd_par_s035/
Dlcd_par_s035_8080.overlay44 width = <480>;

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